Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Timing annotated targets for post-syn sim + docs #856

Merged
merged 2 commits into from
Apr 19, 2021
Merged

Conversation

harrisonliew
Copy link
Contributor

Related issue:
Timing-annotated post-synthesis simulation targets were not configured and documentation for how to use all the sim/power targets was missing. Small clarification to ASAP7 PDK & compatible tool versions.

Type of change: other enhancement

Impact: other

Release Notes

Added post-synthesis timing-annotated sim targets

Copy link
Contributor

@colinschmidt colinschmidt left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM aside from the one typo.

vlsi/sim.mk Outdated Show resolved Hide resolved
vlsi/sim.mk Outdated Show resolved Hide resolved

* Note: this will run ``sim-par`` first

* ``redo-`` can be appended to all above targets to break dependency tracking, like described above.

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I wonder if here could elaborate a little more on what exactly is the dependency it is tracking. Is it the synthesis file or the place and round result. (or it might be a dumb question because i didn't understand the tools well enough)

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It's the flow needed up to the sim point. E.g. post-syn sim depends on synthesis. post-par sim depends on P&R, which also depends on synthesis. Breaking dependency is exactly as it sounds - it allows you to run it without depending on any previous actions.

@harrisonliew harrisonliew merged commit 7f78d77 into dev Apr 19, 2021
@harrisonliew harrisonliew deleted the vlsi-sim-update branch April 19, 2021 17:48
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants