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Fix IOCell generation for clock and reset to use IOCellKey #824

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Mar 11, 2021
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Fix IOCell generation for clock and reset to use IOCellKey #824

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5 changes: 3 additions & 2 deletions generators/chipyard/src/main/scala/Clocks.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ import barstools.iocell.chisel._
import testchipip.{TLTileResetCtrl}

import chipyard.clocking._
import chipyard.iobinders._

/**
* A simple reset implementation that punches out reset ports
Expand All @@ -25,7 +26,7 @@ object GenerateReset {
implicit val p = chiptop.p
// this needs directionality so generateIOFromSignal works
val async_reset_wire = Wire(Input(AsyncReset()))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset",
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset", p(IOCellKey),
abstractResetAsAsync = true)

chiptop.iocells ++= resetIOCell
Expand Down Expand Up @@ -94,7 +95,7 @@ object ClockingSchemeGenerators {
InModuleBody {
val clock_wire = Wire(Input(Clock()))
val reset_wire = GenerateReset(chiptop, clock_wire)
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock")
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
chiptop.iocells ++= clockIOCell

referenceClockSource.out.unzip._1.map { o =>
Expand Down