Code

AXI Memory Over TL Serial Link#812

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Merged

abejgonzalez merged 34 commits intodevucb-bar/chipyard:devfrom offchip-axi-setupucb-bar/chipyard:offchip-axi-setupCopy head branch name to clipboardMar 23, 2021

+585-151

Commits

Commits on Feb 27, 2021

• Small comments to Clocks.scala

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Commits on Feb 28, 2021

• First attempt at getting Offchip AXI port

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Commits on Mar 3, 2021

• Enlarge serial width | Bugfix loadmem disable | Add TracerV

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• General renaming / cleanup

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• Fix FireChip compilation | Remove extra DefaultSerialTL in bridges

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• Cleanup | Fix BlockDevice clocking issues

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Commits on Mar 4, 2021

• Slightly cleaner implementation

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Commits on Mar 5, 2021

• Add support for harness pll

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• 1st pass at connecting to harness PLL | Put UART adapter on harnessClock/Reset

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• Cleanup config + fragments | Remove reference clk div/rst catch in harness [ci skip]

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Commits on Mar 6, 2021

• Distinguish between implicit clock/reset and reference harnessClock/Reset | Don't use parameter system to pass referenceFreq

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Commits on Mar 8, 2021

• Update FireSim to support harness clocks | Small config renaming

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• Renaming updates | Have FireSim clocks request frequency by default

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Commits on Mar 9, 2021

• First doc pass (no updated imgs) [ci skip]

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• Update doc images [ci skip]

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• Merge remote-tracking branch 'origin/dev' into offchip-axi-setup

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  ed6d10a

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• Fix docs harness binders reference

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Commits on Mar 10, 2021

• Clean up the chip communication docs a bit more [ci skip]

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Commits on Mar 11, 2021

• Allow the PLL to request the max freq

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• More clarifications on harness clocks

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Commits on Mar 15, 2021

• Small renaming/cleanup | Use LinkedHashMaps

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• Small renaming in docs

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Commits on Mar 17, 2021

• Use def instead of var Option for ref frequency

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Commits on Mar 19, 2021

• Merge remote-tracking branch 'origin/dev' into offchip-axi-setup

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  7b7bcf7

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• Small spacing fixes

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  4a56508

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• Update docs/Advanced-Concepts/Chip-Communication.rst

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Commits on Mar 20, 2021

• Splitting up FireSim default frequencies into a separate config frag.

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• Allow run-asm/bmark debug make targets to specify random seed

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• Fix TileResetCtrl so that tiles come out of reset after rest of uncore

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• Merge branch 'offchip-axi-setup' of github.com:ucb-bar/chipyard into offchip-axi-setup

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• Bump testchipip

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• Use async queue to connect serdesser + other components

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Commits on Mar 21, 2021

• Bump testchipip

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Commits on Mar 22, 2021

• Update harnessClk/Rst naming to buildtop | Small docs cleanup

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