Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Use "tile" instead of "core" to assign freq's in WithTileFrequency config. fragment #807

Merged
merged 1 commit into from
Mar 3, 2021
Merged
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/ConfigFragments.scala
Original file line number Diff line number Diff line change
Expand Up @@ -193,7 +193,7 @@ class WithTLBackingMemory extends Config((site, here, up) => {
case ExtTLMem => up(ExtMem, site) // enable TL backing memory
})

class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)
class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("tile", fMHz)

class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble
Expand Down