Skip to content

Navigation Menu

Explore
By company size
By use case
By industry
View all solutions
Topics
- AI
- DevOps
- Security
- Software Development
- View all
Explore
- GitHub Sponsors
  Fund open source developers
- The ReadME Project
  GitHub community articles
Repositories
- Enterprise platform
  AI-powered developer platform
Available add-ons
Pricing

Search code, repositories, users, issues, pull requests...

Search

Clear

Search syntax tips

Provide feedback

We read every piece of feedback, and take your input very seriously.

Include my email address so I can be contacted

Saved searches

Use saved searches to filter your results more quickly

Name

Query

To see all available qualifiers, see our documentation.

You signed in with another tab or window. Reload to refresh your session. You signed out in another tab or window. Reload to refresh your session. You switched accounts on another tab or window. Reload to refresh your session.

Dismiss alert

ucb-bar / chipyard Public

Notifications You must be signed in to change notification settings
Fork 674
Star 1.7k

Code
Issues 186
Pull requests 35
Discussions
Actions
Projects
Security
Insights

Additional navigation options

Code
Issues
Pull requests
Discussions
Actions
Projects
Security
Insights

Passing MBus clock frequency to SimDRAM#790

Merged

jerryz123 merged 4 commits intodevucb-bar/chipyard:devfrom simdram_timingsucb-bar/chipyard:simdram_timingsCopy head branch name to clipboard

Feb 18, 2021

+29-4

Conversation Commits4 (4)Checks Files changed

Commits

Commits on Feb 8, 2021

Passing MBus clock frequency to SimDRAM
jerryz123
committed
Add support for manually adjusting DRAM latency with a ShiftQueue
jerryz123
committed
Give TraceGenConfigs an explicit mbus clock
jerryz123
committed

Commits on Feb 9, 2021

Use series of pipe Queues instead of ShiftQueue for adding AXI4 memory delay
jerryz123
committed

Footer

© 2025 GitHub, Inc.

Footer navigation

Terms
Privacy
Security
Status
Docs
Contact

You can’t perform that action at this time.