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Bump TestChipIp to improve default serial_tl behavior #1435

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merged 1 commit into from
Apr 18, 2023
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Bump TestChipIp to improve default serial_tl behavior #1435

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1 change: 0 additions & 1 deletion generators/chipyard/src/main/scala/config/ChipConfigs.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,6 @@ class ChipLikeQuadRocketConfig extends Config(
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new testchipip.WithSerialTLAsyncResetQueue ++ // Add Async reset queue to block ready while in reset

new chipyard.config.AbstractConfig)

2 changes: 1 addition & 1 deletion generators/testchipip
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Submodule testchipip updated 4 files
+1 −0 src/main/resources/testchipip/csrc/blkdev.cc
+1 −0 src/main/resources/testchipip/csrc/plusarg_file_mem.cc
+0 −4 src/main/scala/Configs.scala
+8 −20 src/main/scala/SerialAdapter.scala