Merge pull request #807 from ucb-bar/tile_clk_assignment_fix

Use "tile" instead of "core" to assign freq's in WithTileFrequency config. fragment
ucb-bar · Mar 3, 2021 · a165763 · a165763
2 parents 43a408e + 6145b1d
commit a165763
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala
@@ -204,7 +204,7 @@ class WithTLBackingMemory extends Config((site, here, up) => {
   case ExtTLMem => up(ExtMem, site) // enable TL backing memory
 })
 
-class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)
+class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("tile", fMHz)
 
 class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
   case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble