Merge pull request #806 from ucb-bar/fpga-proto-gpio-pullups

FPGA Prototype - Support Adding Pullup R's to Bringup GPIOs
ucb-bar · Feb 26, 2021 · 8d8506d · 8d8506d
2 parents 86fef9a + 9957538
commit 8d8506d
Show file tree

Hide file tree

Showing 2 changed files with 17 additions and 16 deletions.
diff --git a/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala b/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala
@@ -3,21 +3,21 @@ package chipyard.fpga.vcu118.bringup
 import scala.collection.mutable.{LinkedHashMap}
 
 object BringupGPIOs {
-    // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD)
+    // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD, add pullup resistor?)
     val pinMapping = LinkedHashMap(
         // these connect to LEDs and switches on the VCU118 (and use 1.2V)
-        "led0"  -> ("AT32", "LVCMOS12"), // 0
-        "led1"  -> ("AV34", "LVCMOS12"), // 1
-        "led2"  -> ("AY30", "LVCMOS12"), // 2
-        "led3"  -> ("BB32", "LVCMOS12"), // 3
-        "led4"  -> ("BF32", "LVCMOS12"), // 4
-        "led5"  -> ("AU37", "LVCMOS12"), // 5
-        "led6"  -> ("AV36", "LVCMOS12"), // 6
-        "led7"  -> ("BA37", "LVCMOS12"), // 7
-        "sw0"   -> ("B17", "LVCMOS12"), // 8
-        "sw1"   -> ("G16", "LVCMOS12"), // 9
-        "sw2"   -> ("J16", "LVCMOS12"), // 10
-        "sw3"   -> ("D21", "LVCMOS12") // 11
+        "led0"  -> ("AT32", "LVCMOS12", false), // 0
+        "led1"  -> ("AV34", "LVCMOS12", false), // 1
+        "led2"  -> ("AY30", "LVCMOS12", false), // 2
+        "led3"  -> ("BB32", "LVCMOS12", false), // 3
+        "led4"  -> ("BF32", "LVCMOS12", false), // 4
+        "led5"  -> ("AU37", "LVCMOS12", false), // 5
+        "led6"  -> ("AV36", "LVCMOS12", false), // 6
+        "led7"  -> ("BA37", "LVCMOS12", false), // 7
+        "sw0"   -> ("B17", "LVCMOS12", false), // 8
+        "sw1"   -> ("G16", "LVCMOS12", false), // 9
+        "sw2"   -> ("J16", "LVCMOS12", false), // 10
+        "sw3"   -> ("D21", "LVCMOS12", false) // 11
     )
 
     // return list of names (ordered)

diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
@@ -94,14 +94,15 @@ class BringupGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name:
     require(gpioNames.length == io.gpio.length)
 
     val packagePinsWithIOStdWithPackageIOs = (gpioNames zip io.gpio).map { case (name, io) =>
-      val (pin, iostd) = BringupGPIOs.pinMapping(name)
-      (pin, iostd, IOPin(io))
+      val (pin, iostd, pullupEnable) = BringupGPIOs.pinMapping(name)
+      (pin, iostd, pullupEnable, IOPin(io))
     }
 
-    packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, io) => {
+    packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, pullupEnable, io) => {
       shell.xdc.addPackagePin(io, pin)
       shell.xdc.addIOStandard(io, iostd)
       if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") }
+      if (pullupEnable) { shell.xdc.addPullup(io) }
     } }
   } }
 }