Bump testchipip

ucb-bar · Mar 21, 2021 · 5ffad32 · 5ffad32
1 parent 5526397
commit 5ffad32
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Showing 4 changed files with 4 additions and 3 deletions.
diff --git a/.circleci/config.yml b/.circleci/config.yml
@@ -308,6 +308,7 @@ jobs:
                 tools-version: "esp-tools"
                 group-key: "group-accels"
                 project-key: "chipyard-hwacha"
+                timeout: "30m"
     chipyard-gemmini-run-tests:
         executor: main-env
         steps:

diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -130,7 +130,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
         val harnessMultiClockAXIRAM = withClockAndReset(th.harnessClock, th.harnessReset) {
           SerialAdapter.connectHarnessMultiClockAXIRAM(
             system.serdesser.get,
-            port,
+            serial_bits,
             axiClockBundle,
             th.harnessReset)
         }

diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -95,7 +95,7 @@ class WithFireSimDefaultFrequencyTweaks extends Config(
   // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values.
   new chipyard.config.WithMemoryBusFrequency(1000.0) ++
   new chipyard.config.WithAsynchrousMemoryBusCrossing ++
-  new testchipip.WithAsynchronousSerialSlaveCrossing ++
+  new testchipip.WithAsynchronousSerialSlaveCrossing
 )
 
 // Tweaks that are generally applied to all firesim configs

diff --git a/generators/testchipip b/generators/testchipip