Initial stab at adding verilog testbench generator for jtag #8
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grebe
commented
Apr 11, 2017
| .io_jtag_TDO_data(tdo) | ||
| ); | ||
| `else | ||
| tms = 1'b0; |
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If I build sim or debug, it doesn't like these lines. Am I being dumb? Why isn't this OK
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I'm not sure you can hook up a reg to a port. Make them wires. If you need regs, have assign statements or something.
grebe
commented
Apr 11, 2017
| @@ -20,5 +20,6 @@ trait JTAGTestLevelIO { | |||
| val tdi = Input(Bool()) | |||
| val tdo = Output(Bool()) | |||
| val tclk = Input(Bool()) | |||
| val tdo_driven = Output(Bool()) | |||
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Rather than doing this, I should have a variable in the test driver that checks if tdo is Z. Do you know how to do this @stevobailey?
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Yeah, there's an always block in the TestDriver that ticks on the core clock. You can add some wires and hook them up to the JTAG inputs/outputs.
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Don't merge- depends on ucb-art/dsp-framework#18.