[stevo]: commit changes to date

Makefrag

@@ -34,7 +34,7 @@ PROJECT ?= craft
 MODEL ?= TestHarness
 CFG_PROJECT ?= $(PROJECT)
 CONFIG ?= AcmesConfig
-VLSICORE ?= CraftP1CoreTop
+VLSICORE ?= CraftP1Core
 VLSITOP ?= CraftP1Top
 VLSIPADS ?= CraftP1Pads
 TB ?= TestDriver
@@ -63,7 +63,7 @@ $(build_dir)/$(long_name).v $(build_dir)/$(long_name).harness.v $(build_dir)/$(l
 	cd $(base_dir) && $(SBT) "runMain barstools.tapeout.transforms.GenerateTopAndHarness -i $< --top-o $(build_dir)/$(long_name).v --harness-o $(build_dir)/$(long_name).harness.v --syn-top $(VLSICORE) --harness-top $(MODEL) --seq-mem-flags \"-o:$(build_dir)/$(long_name).conf\" --list-clocks \"-o:$(build_dir)/$(long_name).domains\" --anno-file $(build_dir)/$(long_name).anno" 
 
 $(build_dir)/$(long_name).mems.v: $(build_dir)/$(long_name).conf $(MEM_GEN) $(FLOP_GEN) $(SRAMS)
-	cd $(build_dir) && $(MEM_GEN) -conf=$(build_dir)/$(long_name).conf -srams=$(SRAMS) -flop=$(FLOP_GEN) -v=$(build_dir)/$(long_name).mems.v -report=$(build_dir)/$(long_name).mems.rpt -ff True
+	cd $(build_dir) && $(MEM_GEN) -conf=$(build_dir)/$(long_name).conf -srams=$(SRAMS) -flop=$(FLOP_GEN) -v=$(build_dir)/$(long_name).mems.v -report=$(build_dir)/$(long_name).mems.rpt
 
 ## [stevo]: temporary hack to rename dut from Core to Top so it includes the pad frame, and add rte
 #$(build_dir)/$(long_name).top.v $(build_dir)/$(long_name).io $(build_dir)/$(long_name).pads.v $(build_dir)/pads.behav.v: $(build_dir)/$(long_name).mems.v $(PAD_GEN) $(HARNESS_MOD)

fpga_setup.sh

@@ -0,0 +1,9 @@
+cp generated-src/craft.TestHarness.AcmesFPGAConfig.v /tools/projects/stevo/acmes/acmes-fpga-testing/zc706/src/verilog/CraftP1Core.ZynqConfig.v
+cat generated-src/craft.TestHarness.AcmesFPGAConfig.mems.v >> /tools/projects/stevo/acmes/acmes-fpga-testing/zc706/src/verilog/CraftP1Core.ZynqConfig.v
+cat vsrc/AsyncResetReg.v >> /tools/projects/stevo/acmes/acmes-fpga-testing/zc706/src/verilog/CraftP1Core.ZynqConfig.v
+sed "s|Arbiter|StevoArbiter|g" -i /tools/projects/stevo/acmes/acmes-fpga-testing/zc706/src/verilog/CraftP1Core.ZynqConfig.v
+sed "s|Queue|StevoQueue|g" -i /tools/projects/stevo/acmes/acmes-fpga-testing/zc706/src/verilog/CraftP1Core.ZynqConfig.v
+sed "s|Async|StevoAsync|g" -i /tools/projects/stevo/acmes/acmes-fpga-testing/zc706/src/verilog/CraftP1Core.ZynqConfig.v
+sed "s|Nasti|StevoNasti|g" -i /tools/projects/stevo/acmes/acmes-fpga-testing/zc706/src/verilog/CraftP1Core.ZynqConfig.v
+sed "s|IdMapper|StevoIdMapper|g" -i /tools/projects/stevo/acmes/acmes-fpga-testing/zc706/src/verilog/CraftP1Core.ZynqConfig.v
+sed "s|SCRFile|StevoSCRFile|g" -i /tools/projects/stevo/acmes/acmes-fpga-testing/zc706/src/verilog/CraftP1Core.ZynqConfig.v

ncsim/Makefile

@@ -22,11 +22,12 @@ sim_vsrcs = \
 	$(base_dir)/vsrc/des72to288.v \
 	$(base_dir)/raven3_lvss/verilog/RAVEN3_LVSS.v \
 	$(base_dir)/vsrc/AsyncResetReg.v \
-	/tools/stalpha/cmos28fdsoi_29/C28SOI_SPHD_BB_180207A/4.4-01.00/behaviour/verilog/SPHD_BB_180207A.v \
-	/tools/stalpha/cmos28fdsoi_29/C28SOI_SPHD_BB_180207B/4.4-00.00/behaviour/verilog/SPHD_BB_180207B.v \
-	/tools/stalpha/cmos28fdsoi_29/C28SOI_SPHD_BB_180207C/4.4-01.00/behaviour/verilog/SPHD_BB_180207C.v \
-	/tools/stalpha/cmos28fdsoi_29/C28SOI_DPREG_BB_180207/4.4-00.00/behaviour/verilog/DPREG_BB_180207.v \
-	/tools/stalpha/cmos28fdsoi_29/C28SOI_SPREG_BB_180207/4.4-00.00/behaviour/verilog/SPREG_BB_180207.v \
+	/tools/stalpha/cmos28fdsoi_29/C28SOI_SPHD_HIPERF_180502A/4.6-00.00/behaviour/verilog/SPHD_HIPERF_180502A.v \
+	/tools/stalpha/cmos28fdsoi_29/C28SOI_DPREG_HIPERF_180502/4.5-00.00/behaviour/verilog/DPREG_HIPERF_180502.v \
+  /tools/stalpha/cmos28fdsoi_29/C28SOI_SPHD_HIPERF_180502B/4.6-00.00/behaviour/verilog/SPHD_HIPERF_180502B.v \
+	/tools/stalpha/cmos28fdsoi_29/C28SOI_SPREG_LOLEAK_180502A/4.5-00.00/behaviour/verilog/SPREG_LOLEAK_180502A.v \
+  /tools/stalpha/cmos28fdsoi_29/C28SOI_SPREG_LOLEAK_180502B/4.5-00.00/behaviour/verilog/SPREG_LOLEAK_180502B.v \
+	/tools/stalpha/cmos28fdsoi_29/C28SOI_SPREG_LOLEAK_180502C/4.5-00.00/behaviour/verilog/SPREG_LOLEAK_180502C.v \
 
 
 sim_csrcs = \

src/main/scala/craft/ADC.scala

@@ -74,17 +74,17 @@ class TISARADC extends BlackBox {
 
 class DeserIO extends Bundle {
   val in           = Input(Vec(8, UInt(9.W)))
-  val out          = Output(Vec(32, UInt(9.W)))
+  val out          = Output(Vec(64, UInt(9.W)))
   val clk          = Input(Clock())
   val rst          = Input(Bool())
   // clock that follows data to fifo
   val clkout_data = Output(Clock())
   // clock that goes to rest of the dsp chain
   val clkout_dsp = Output(Clock())
   // set the phase during reset
-  val phi_init = Input(UInt(2.W))
+  val phi_init = Input(UInt(3.W))
 }
 
-class des72to288 extends BlackBox {
+class des72to576 extends BlackBox {
   val io = IO(new DeserIO)
 }

src/main/scala/craft/Accumulator.scala

@@ -193,8 +193,8 @@ class Accumulator[T <: Data:Real]()(implicit val p: Parameters) extends Module w
   val accum_in = Vec(in.zip(io.out.bits).map { case (i, o) => Mux(sState != sAccum, i, DspContext.withOverflowType(dsptools.Wrap) {o+i} ) })
   // TODO : undo this when real SRAMs are available 
   // [stevo]: large SRAMs have max width of 64; there is a 512x128 though, so if the depth is 512, this should be combined
-  io.out.bits.zip(accum_in).foreach { case (out,in) =>
-    out := ShiftRegisterMem(in, config.outputWindowSize/lanes_new, accum)
+  io.out.bits.zip(accum_in).foreach { case (o,i) =>
+    o := ShiftRegisterMem(i, config.outputWindowSize/lanes_new, accum)
   }
   //io.out.bits := ShiftRegisterMem(accum_in, config.outputWindowSize/lanes_new, accum)
 }

src/main/scala/craft/Configs.scala

@@ -45,7 +45,7 @@ object ChainBuilder {
 
   def acmes(id: String = "acmes", channels: Int = 64): Config = {
 
-    val lanes = 32
+    val lanes = 64
     val numTaps = 4
     val quadrature = true
 
@@ -54,48 +54,48 @@ object ChainBuilder {
     def bm1Input():T = FixedPoint(9.W, 0.BP)
     def bm1Output():T = FixedPoint(9.W, 0.BP)
     def bm1Connect() = BlockConnectionParameters(connectPG = true, connectLA = true, addSAM = false)
-    def bm1SAMConfig() = Some(SAMConfig(subpackets = 1, bufferDepth = 1024)) // TODO was 4096
+    def bm1SAMConfig() = Some(SAMConfig(subpackets = 1, bufferDepth = 1024)) // not used
 
     // Here be the filterbank
     // notes on windows: the sincHamming doesn't go to zero on the edges, so Hanning is preferred
     val pd = if (quadrature) channels/(lanes/2)*(numTaps-1) else channels/lanes*(numTaps-1)
     def pfbConfig() = PFBConfig(windowFunc = sincHanning.apply, processingDelay = pd, numTaps = numTaps, outputWindowSize = channels, lanes = lanes, multiplyPipelineDepth = 1, outputPipelineDepth = 1, genTap = Some(pfbTap), quadrature = quadrature)
     def pfbInput():T = FixedPoint(9.W, 8.BP)
     // [stevo]: make sure pfbTap and pfbConvert use the same width and binary point
-    def pfbTap:T = FixedPoint(10.W, 7.BP)
-    def pfbConvert(x: Double):T = FixedPoint.fromDouble(x, 10.W, 7.BP)
-    def pfbOutput():T = FixedPoint(12.W, 8.BP)
+    def pfbTap:T = FixedPoint(9.W, 8.BP)
+    def pfbConvert(x: Double):T = FixedPoint.fromDouble(x, 9.W, 8.BP)
+    def pfbOutput():T = FixedPoint(12.W, 7.BP) // loss of 1 LSB precision
     def pfbConnect() = BlockConnectionParameters(connectPG = true, connectLA = true, addSAM = false)
-    def pfbSAMConfig() = Some(SAMConfig(subpackets = 1, bufferDepth = 1024)) // TODO was 4096
+    def pfbSAMConfig() = Some(SAMConfig(subpackets = 1, bufferDepth = 1024)) // not used
 
     // Here be the Fourier transform
     def fftConfig() = FFTConfig(n = channels, lanes = lanes, pipelineDepth = 13, real = true, quadrature = quadrature)
-    def fftInput():T = FixedPoint(12.W, 8.BP) // gets complexed automatically
-    def fftOutput():T = FixedPoint(18.W, 8.BP) // gets complexed automatically
+    def fftInput():T = FixedPoint(12.W, 7.BP) // gets complexed automatically
+    def fftOutput():T = FixedPoint(18.W, 6.BP) // gets complexed automatically // loss of 1 LSB precision, plus only 1 bit growth every other stage
     def fftConnect() = BlockConnectionParameters(connectPG = true, connectLA = true, addSAM = false)
-    def fftSAMConfig() = Some(SAMConfig(subpackets = 1, bufferDepth = 1024)) // TODO was 4096
+    def fftSAMConfig() = Some(SAMConfig(subpackets = 1, bufferDepth = 1024)) // not used
 
     // Here be the cross calibration block
     def ccConfig() = CrossCalibrateConfig(channels = channels, lanes = lanes, pipelineDepth = 1)
-    def ccInput():T = FixedPoint(18.W, 8.BP) // gets complexed automatically
+    def ccInput():T = FixedPoint(18.W, 6.BP) // gets complexed automatically
     // note: as a hack, the calibration coefficient bitwidth is set in the CrossCalibrate file as 2 total bits less than the input bitwidth (same fractional width)
-    def ccOutput():T = FixedPoint(18.W, 8.BP) // gets complexed automatically
+    def ccOutput():T = FixedPoint(18.W, 6.BP) // gets complexed automatically
     def ccConnect() = BlockConnectionParameters(connectPG = true, connectLA = true, addSAM = false)
-    def ccSAMConfig() = Some(SAMConfig(subpackets = 1, bufferDepth = 1024)) // TODO was 4096
+    def ccSAMConfig() = Some(SAMConfig(subpackets = 1, bufferDepth = 1024)) // not used
 
     // Here be the power block
     def powerConfig() = PowerConfig(lanes = lanes, pipelineDepth = 1, quadrature = quadrature)
-    def powerInput():T = FixedPoint(18.W, 8.BP) // gets complexed automatically
-    def powerOutput():T = FixedPoint(36.W, 8.BP)
+    def powerInput():T = FixedPoint(18.W, 6.BP) // gets complexed automatically
+    def powerOutput():T = FixedPoint(34.W, 10.BP) // loss of 3 LSB precision?
     def powerConnect() = BlockConnectionParameters(connectPG = true, connectLA = true, addSAM = false)
-    def powerSAMConfig() = Some(SAMConfig(subpackets = 1, bufferDepth = 1024)) // TODO was 4096
+    def powerSAMConfig() = Some(SAMConfig(subpackets = 1, bufferDepth = 1024)) // not used
 
     // Here be the accumulator block
     def accumConfig() = AccumulatorConfig(lanes = lanes, outputWindowSize = channels, maxSpectra = 2048, quadrature = quadrature)
-    def accumInput():T = FixedPoint(36.W, 8.BP)
-    def accumOutput():T = FixedPoint(64.W, 8.BP)
+    def accumInput():T = FixedPoint(34.W, 10.BP)
+    def accumOutput():T = FixedPoint(64.W, 10.BP)
     def accumConnect() = BlockConnectionParameters(connectPG = true, connectLA = false, addSAM = true)
-    def accumSAMConfig() = Some(SAMConfig(subpackets = 1, bufferDepth = 512)) // TODO was 4096 then 512
+    def accumSAMConfig() = Some(SAMConfig(subpackets = 1, bufferDepth = 256)) // one spectrum
 
   ///////////////////////////////////////////////////////////////
   ////////////                                     Here be acmes 
@@ -115,11 +115,11 @@ object ChainBuilder {
             (implicit p => new PowerBlock[T], id + ":power", powerConnect(), powerSAMConfig()),
             (implicit p => new AccumulatorBlock[T], id + ":accum", accumConnect(), accumSAMConfig())
           ),
-          logicAnalyzerSamples = 8192, 
-          logicAnalyzerUseCombinationalTrigger = true, 
-          patternGeneratorSamples = 8192, // TODO what should it be? was 8192
+          logicAnalyzerSamples = 256, // one spectrum...hopefully it's enough?
+          logicAnalyzerUseCombinationalTrigger = true,
+          patternGeneratorSamples = 256, // one spectrum...hopefully it's enough?
           patternGeneratorUseCombinationalTrigger = true,
-          biggestWidth = 2048
+          biggestWidth = 4096
         )
         case _ => throw new CDEMatchError
       }
@@ -151,25 +151,28 @@ class WithMiniSerialAdapter extends Config(
 //)
 
 class AcmesBaseConfig extends Config(
+  new WithDma ++
   new WithL2Capacity(512) ++
   new WithL2Cache ++
-  new WithExtMemSize(8L * 1024L * 1024L) ++
+  new WithExtMemSize(1L * 1024L * 1024L) ++
+  new WithNL2AcquireXacts(4) ++ 
   new WithNMemoryChannels(8) ++
   new WithSRAM(4) ++
-  new WithDma ++
+  //new WithSRAM(1) ++
   new WithMiniSerialAdapter ++
   new rocketchip.BaseConfig)
 
 class AcmesTinyBaseConfig extends Config(
+  new WithDma ++
   new WithL2Capacity(8) ++
   new WithL2Cache ++
   new WithExtMemSize(256L * 1024L) ++
+  new WithNL2AcquireXacts(4) ++ 
   new WithNMemoryChannels(8) ++
   new WithSRAM(4) ++
-  new WithDma ++
   new WithMiniSerialAdapter ++
   new rocketchip.BaseConfig)
 
-class AcmesConfig extends Config(ChainBuilder.acmes(channels=64) ++ new AcmesBaseConfig)
+class AcmesConfig extends Config(ChainBuilder.acmes(channels=8192) ++ new AcmesBaseConfig)
 class AcmesTinyConfig extends Config(ChainBuilder.acmes(channels=64) ++ new AcmesTinyBaseConfig)
-class AcmesFPGAConfig extends Config(ChainBuilder.acmes(channels=64) ++ new AcmesTinyBaseConfig)
+class AcmesFPGAConfig extends Config(ChainBuilder.acmes(channels=256) ++ new AcmesTinyBaseConfig)

src/main/scala/craft/Craft2DSP.scala

@@ -73,7 +73,8 @@ trait PeripheryCraft2DSPModule extends HasPeripheryParameters {
 
   val craftChainModule = craftChain.module
 
-  val dsp_clock = craftChainModule.io.adc_clk_out
+  //val dsp_clock = craftChainModule.io.adc_clk_out
+  val dsp_clock = io.ADCCLKP.asClock
   val dsp_reset = ResetSync(io.dsp_reset, dsp_clock)
   craftChainModule.clock := dsp_clock
   craftChainModule.reset := dsp_reset

src/main/scala/craft/DspChainWithADC.scala

@@ -138,7 +138,7 @@ trait ADCModule {
     adc.io.adcout6,
     adc.io.adcout7)
 
-  lazy val deser = Module(new des72to288)
+  lazy val deser = Module(new des72to576)
   deser.io.in := adcout
   deser.io.clk := adc.io.clkout_des
   // [stevo]: wouldn't do anything, since it's only used on reset
@@ -153,10 +153,7 @@ trait ADCModule {
   // this lazy weirdness is needed because other traits look at streamIn
   // before this code executes
 
-  // no ADC calibration
   lazy val numInBits = 9
-  lazy val numOutBits = 9
-  lazy val numSlices = 8*4
 
   // convert unsigned to signed
   lazy val streamIn = Wire(ValidWithSync(des_sync.asTypeOf(UInt())))