Implement Zve32x Vector Integer Arithmetic Instructions

[danielschloms]

This PR implements the vector integer arithmetic instructions according to the RVV spec version 1.0. Testing was done using the relevant rv32uv tests from this repository. Therefore, the functionality for EEW = 64 is untested.

[PhilippvK]

@danielschloms Did you also add new test cases/files to the test suite by any chance? Can you give an estimate on how many of the vector integer arithmetic instructions are covered by at least one test case?

[PhilippvK]

@danielschloms Do you need help setting up an etiss architecture to test the Zve64x support as well?

[danielschloms]

@danielschloms Did you also add new test cases/files to the test suite by any chance? Can you give an estimate on how many of the vector integer arithmetic instructions are covered by at least one test case?

Are you talking about the golden tests in the softvector repo or your riscv-tests fork? As for the the softvector test suite, only a small set of instructions is covered (add, sub, unitstride load/store, mul(h/hu/hsu), and, or, xor, and single width shifts). Would you like that all instructions are also covered by the softvector test suite? The other repo did cover all vector integer arithmetic instructions, but some others are missing, e.g. vnclip(u).

@danielschloms Do you need help setting up an etiss architecture to test the Zve64x support as well?

That would be great :)

[PhilippvK]

Are you talking about the golden tests in the softvector repo or your riscv-tests fork?

I was interested in both.

As for the the softvector test suite, only a small set of instructions is covered (add, sub, unitstride load/store, mul(h/hu/hsu), and, or, xor, and single width shifts). Would you like that all instructions are also covered by the softvector test suite?

Yes at some point (but probably out of scope for this PR)

The other repo did cover all vector integer arithmetic instructions, but some others are missing, e.g. vnclip(u).

thanks for the clarification. I saw that recently a few new test suites for RVV showed up, probably with greater coverage. Would probably be a good idea to try it out at some point: https://github.com/chipsalliance/riscv-vector-tests

That would be great :)

I am out of office until next Thursday, but we can arrange something when I am back :)

[PhilippvK]

@danielschloms Sorry for the delay!

I created a RVV 64-bit ETISS arch and pushed it here: https://github.com/PhilippvK/etiss/tree/rvv-2024-new
I guess that you have you own etiss fork with different changes, but you can probably cherry-pick/copy the relevant patches.

I couldn't check check if the generated RV64 arch passes any tests in the test suite. You will probably download a rv64 riscv-gcc and recompile the test-cases with XLEN=64. Please let me know if you need further advice...

[PhilippvK]

Merging this now. RV64 support should be addressed in a new PR.