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etiss: add comments on simple_mem_system.memseg_mode_*
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PhilippvK committed May 29, 2024
1 parent ed66f54 commit 7cde237
Showing 1 changed file with 3 additions and 0 deletions.
3 changes: 3 additions & 0 deletions mlonmcu/target/riscv/etiss.py
Original file line number Diff line number Diff line change
Expand Up @@ -343,6 +343,9 @@ def get_ini_bool_config(self):
def get_ini_string_config(self):
ret = {
"arch.cpu": self.cpu_arch,
# Mode will be overwritten by elf...
# "simple_mem_system.memseg_mode_00": "RX",
# "simple_mem_system.memseg_mode_01": "RWX",
}
if self.jit is not None:
ret["jit.type"] = f"{self.jit}JIT"
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