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etiss_pulpino: write ini options for mstatus_fs, mstatus_vs, vlen and…
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… elen (unimplemented)
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PhilippvK committed Jul 14, 2022
1 parent 7b27f7c commit 290b0f2
Showing 1 changed file with 25 additions and 0 deletions.
25 changes: 25 additions & 0 deletions mlonmcu/target/etiss_pulpino.py
Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,11 @@ class EtissPulpinoTarget(RISCVTarget):
"etissvp.ram_start": 0x800000,
"etissvp.ram_size": 0x4000000, # 64 MB
"etissvp.cycle_time_ps": 31250, # 32 MHz
"enable_fpu": True, # WIP
"enable_vext": False,
"enable_pext": False,
"vlen": 0, # vectorization=off
"elen": 32,
"jit": None,
}
REQUIRED = RISCVTarget.REQUIRED + ["etiss.src_dir", "etiss.install_dir", "etissvp.script"]
Expand Down Expand Up @@ -132,6 +135,10 @@ def cpu_arch(self):
else:
return "RV32IMACFD"

@property
def enable_fpu(self):
return bool(self.config["enable_fpu"])

@property
def enable_vext(self):
return bool(self.config["enable_vext"])
Expand All @@ -140,6 +147,14 @@ def enable_vext(self):
def enable_pext(self):
return bool(self.config["enable_pext"])

@property
def vlen(self):
return int(self.config["vlen"])

@property
def elen(self):
return int(self.config["elen"])

@property
def jit(self):
return self.config["jit"]
Expand Down Expand Up @@ -175,6 +190,16 @@ def write_ini(self, path):
f.write(f"simple_mem_system.memseg_length_01={hex(self.ram_size)}\n")
f.write("\n")
f.write(f"arch.cpu_cycle_time_ps={self.cycle_time_ps}\n")
if self.enable_fpu:
# TODO: do not hardcode cpu_arch
# TODO: i.e. use cpu_arch_lower
f.write(f"arch.rv32imacfdpv.mstatus_fs=1")
if self.enable_vext:
f.write(f"arch.rv32imacfdpv.mstatus_vs=1")
if self.vlen > 0:
f.write(f"arch.rv32imacfdpv.vlen={self.vlen}")
# if self.elen > 0:
# f.write(f"arch.rv32imacfdpv.elen={self.elen}")

if self.gdbserver_enable:
f.write("[Plugin gdbserver]\n")
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