Merge upstream #2
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Patched erroneous assembly statement for CADDI4SPN instruction
| X[rd % RFS] = (unsigned<XLEN>)(signed<32>)((signed<32>)X[rs1 % RFS] * (signed<32>)X[rs2 % RFS]); | ||
| } | ||
| behavior: if(rd >=RFS || rs1>=RFS || rs2>=RFS) raise(0, 2); else { | ||
| if(rd!=0) X[rd] = (signed<64>)((signed<32>)X[rs1] * (signed<32>)X[rs2]); |
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will also break on 128 bit cores; also signed / unsigned assignment
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@wysiwyng I would appreciate it if you could have a look at the open threads as well. The RISC-V spec is not really explicit regarding the signedness here. |
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Maybe also @Samanti-Das because some of the "conflicting" changes have been added by you. |
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Look at the comments, there's a few things I disagree with. This is also our development repository, so making pull requests back to upstream is also encouraged. I don't really like the way the RVE handling is done, the old handling |
I am currently looking into this.
In my option most of these illegal instruction exceptions should not be generated in the instructions behavior. There should be a way to specify constrains on fields/operands in the encoding. If you agree with me, I can open up an Issue to discuss that publicly. |
Let's try to keep track with the latest upstream changes. This is a draft because I am not 100% sure about a few merges i did and this is currently untested.
TODO: