Merge branch 'main' into tsvbootloaderchanges

boards/tsi/skyp/Kconfig

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+# config BOARD_TSI
+# 	select QEMU_TARGET

boards/tsi/skyp/Kconfig.defconfig

@@ -0,0 +1,21 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_TSI
+
+# MPU-based null-pointer dereferencing detection cannot
+# be applied as the (0x0 - 0x400) is unmapped but QEMU
+# will still permit bus access.
+choice NULL_POINTER_EXCEPTION_DETECTION
+	bool
+	default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET
+endchoice
+
+if SERIAL
+
+config UART_INTERRUPT_DRIVEN
+	default n
+
+endif # SERIAL
+
+endif

boards/tsi/skyp/Kconfig.tsi

@@ -0,0 +1,7 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_TSI
+	select SOC_PART_NUMBER_MIMX8ML8DVNLZ
+	select SOC_SKYP_M85 if BOARD_TSI_SKYP_M85
+	select SOC_MIMX8ML8_ADSP if BOARD_TSI_SKYP_TXE

boards/tsi/skyp/board.yml

@@ -0,0 +1,10 @@
+board:
+  name: tsi
+  vendor: tsi
+  socs:
+  - name: skyp
+    variants:
+    - name: tensilica
+      cpucluster: txe
+    - name: cortex-m85
+      cpucluster: m85

boards/tsi/skyp/tsi_skyp_m85-common.dtsi

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019-2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ sysclk: system-clock {
+	compatible = "fixed-clock";
+	clock-frequency = <25000000>;
+	#clock-cells = <0>;
+};
+
+uart0: uart@14001000 {
+	compatible = "arm,cmsdk-uart";
+	reg = <0x14001000 0x1000>;
+	interrupts = <34 3 33 3>;
+	interrupt-names = "tx", "rx";
+	clocks = <&sysclk>;
+	current-speed = <115200>;
+};

boards/tsi/skyp/tsi_skyp_m85.dts

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2024 TSI
+ * Copyright 2022 Arm Limited and/or its affiliates <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm/armv8.1-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <mem.h>
+
+/ {
+	compatible = "arm,mps3-an547";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &jtag_uart;
+		zephyr,shell-uart = &jtag_uart;
+		zephyr,sram = &sram;
+		zephyr,flash = &sram0;
+	};
+
+	jtag_uart: uart@95003000 {
+		compatible = "altr,jtag-uart";
+		reg = <0x95003000 0x8>;
+		status = "enabled";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m85";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8.1m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	/* We utilize the secure addresses, if you subtract 0x10000000
+	 * you'll get the non-secure alias
+	 */
+	itcm: itcm@4000 {   /* alias @ 0x4000 */
+		compatible = "zephyr,memory-region";
+		reg = <0x4000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "ITCM";
+	};
+
+	sram0: sram0@60000000 {	/* alias @ 0x60000000 */
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_K(256)>;
+		zephyr,memory-region = "SRAM0";
+	};
+
+	sram: sram@60040000 {	/* alias @ 0x60040000 */
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x60040000 DT_SIZE_K(1792)>;
+		zephyr,memory-region = "SRAM";
+	};
+
+	dtcm: dtcm@20000000 {	/* alias @ 0x20000000 */
+		compatible = "zephyr,memory-region";
+		reg = <0x20000000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	isram: sram@60600000 {/* alias @ 0x60600000 */
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x60600000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "ISRAM";
+	};
+
+	/* DDR4 - 2G, alternates non-secure/secure every 256M */
+	ddr4: memory@60700000 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region";
+		reg = <0x60700000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "DDR4";
+	};
+
+	soc {
+		peripheral@81000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x81000000 0x1effffff>;
+
+			 #include "tsi_skyp_m85-common.dtsi"
+		};
+	};
+};
+
+&jtag_uart {
+	status = "okay";
+	current-speed = <9600>;
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};

boards/tsi/skyp/tsi_skyp_m85.yaml

@@ -0,0 +1,12 @@
+identifier: tsi/skyp/m85
+name: TSI sky-p
+type: mcu
+arch: arm
+ram: 1792
+flash: 256
+simulation: qemu
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+vendor: arm

boards/tsi/skyp/tsi_skyp_m85_defconfig

@@ -0,0 +1,18 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_RUNTIME_NMI=y
+CONFIG_ARM_TRUSTZONE_M=n
+CONFIG_ARM_MPU=y
+CONFIG_QEMU_ICOUNT_SHIFT=7
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+
+# Build a Secure firmware image
+CONFIG_TRUSTED_EXECUTION_SECURE=n
+
+# Build the zephyr.hex and zephyrstrp.hex for FPGA
+CONFIG_BUILD_OUTPUT_TSV_STRIPPED_HEX=y

boards/tsi/skyp/tsi_skyp_txe.dts

@@ -0,0 +1,47 @@
+/*
+ * Copyright 2021, 2023, 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_imx8m.dtsi>
+#include <nxp/nxp_imx/mimx8ml8dvnlz-pinctrl.dtsi>
+
+/ {
+	model = "NXP i.MX 8MPLUS Audio DSP";
+	compatible = "nxp";
+
+	chosen {
+		//zephyr,sram = &sram0;
+		zephyr,sram = &sram_txe;
+
+		zephyr,console = &uart4;
+		zephyr,shell-uart = &uart4;
+	};
+	sram_txe: memory@60040000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x60040000 DT_SIZE_K(512)>;
+	};
+};
+
+&pinctrl {
+	uart4_default: uart4_default {
+		group0 {
+			pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>,
+				<&iomuxc_uart4_txd_uart_tx_uart4_tx>;
+			bias-pull-up;
+			slew-rate = "slow";
+			drive-strength = "x1";
+		};
+	};
+};
+
+&uart4 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart4_default>;
+	pinctrl-names = "default";
+};

boards/tsi/skyp/tsi_skyp_txe.yaml

@@ -0,0 +1,16 @@
+identifier: tsi/skyp/txe
+name: TSI DSP
+type: mcu
+arch: xtensa
+toolchain:
+  - xcc
+  - xt-clang
+  - zephyr
+supported:
+  - uart
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - mcumgr
+vendor: nxp

boards/tsi/skyp/tsi_skyp_txe_defconfig

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# size of stack for initialization and main thread
+CONFIG_MAIN_STACK_SIZE=3072
+
+# enable logger
+CONFIG_LOG=y
+
+# no need for a "raw" binary zephyr/zephyr.bin in the build directory
+CONFIG_BUILD_OUTPUT_BIN=y
+CONFIG_BUILD_OUTPUT_HEX=y
+
+# enable uart driver
+CONFIG_SERIAL=y
+
+# clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# console (remote proc console by default)
+CONFIG_CONSOLE=y
+
+# uart console (overrides remote proc console)
+CONFIG_UART_CONSOLE=y
+
+# enable pin controller
+CONFIG_PINCTRL=y

dts/bindings/vendor-prefixes.txt

@@ -683,6 +683,7 @@ tronfy	Tronfy
 tronsmart	Tronsmart
 truly	Truly Semiconductors Limited
 tsd	Theobroma Systems Design und Consulting GmbH
+tsi	Tsavorite Scalable Intelligence
 tyan	Tyan Computer Corporation
 u-blox	u-blox
 u-boot	U-Boot bootloader

soc/nxp/imx/imx8m/adsp/memory.h

@@ -14,14 +14,21 @@
 
 #define IRAM_RESERVE_HEADER_SPACE	0x400
 
-#define IRAM_BASE	0x3B6F8000
+/*#define IRAM_BASE    0x3B6F8000*/
+#define IRAM_BASE      0x60600000
+#define IRAM_SIZE      0x800
+
 #define IRAM_SIZE	0x800
 
-#define SDRAM0_BASE	0x92400000
-#define SDRAM0_SIZE	0x800000
+/*#define SDRAM0_BASE	0x92400000*/
+/*#define SDRAM0_SIZE	0x800000*/
+#define SDRAM0_BASE    0x60601000
+#define SDRAM0_SIZE	   0xFF000
 
-#define SDRAM1_BASE	0x92C00000
-#define SDRAM1_SIZE	0x800000
+/*#define SDRAM1_BASE	0x92C00000*/
+/*#define SDRAM1_SIZE	0x800000*/
+#define SDRAM1_BASE    0x60700000
+#define SDRAM1_SIZE    0x100000
 
 /* The reset vector address in SRAM and its size */
 #define MEM_RESET_TEXT_SIZE			0x2E0
@@ -36,7 +43,8 @@
 /*
  * EXCEPTIONS and VECTORS
  */
-#define XCHAL_RESET_VECTOR0_PADDR_IRAM	0x3B6F8000
+/*#define XCHAL_RESET_VECTOR0_PADDR_IRAM	0x3B6F8000*/
+#define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x6060000
 
 /* Vector and literal sizes */
 #define MEM_VECT_LIT_SIZE			0x4
@@ -78,20 +86,27 @@
 #define IDT_SIZE	0x2000
 
 /* physical DSP addresses */
-#define IRAM_BASE	0x3B6F8000
+/*#define IRAM_BASE	0x3B6F8000*/
+#define IRAM_BASE   0x60600000
 #define IRAM_SIZE	0x800
 
-#define DRAM0_BASE	0x3B6E8000
-#define DRAM0_SIZE	0x8000
+/*#define DRAM0_BASE	0x3B6E8000*/
+#define DRAM0_BASE	0x70800000
+#define DRAM0_SIZE		0x8000
 
-#define DRAM1_BASE	0x3B6F0000
-#define DRAM1_SIZE	0x8000
+/*#define DRAM1_BASE	0x3B6F0000*/
+#define DRAM1_BASE	0x80608000
+#define DRAM1_SIZE		0x8000
 
-#define SDRAM0_BASE	0x92400000
-#define SDRAM0_SIZE	0x800000
+/*#define SDRAM0_BASE	0x92400000*/
+#define SDRAM0_BASE	0x60601000
+/*#define SDRAM0_SIZE	0x800000*/
+#define SDRAM0_SIZE		0xFF000
 
-#define SDRAM1_BASE	0x92C00000
-#define SDRAM1_SIZE	0x800000
+/*#define SDRAM1_BASE	0x92C00000*/
+#define SDRAM1_BASE     0x60700000
+/*#define SDRAM1_SIZE	0x800000*/
+#define SDRAM1_SIZE     0x100000
 
 #define XSHAL_MU2_SIDEB_BYPASS_PADDR 0x30E70000
 #define MU_BASE		XSHAL_MU2_SIDEB_BYPASS_PADDR

soc/tsi/CMakeLists.txt

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+if(DEFINED SOC_SERIES)
+  add_subdirectory(${SOC_SERIES})
+else()
+  add_subdirectory(${SOC_NAME})
+endif()