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AArch64: fix ldrb size #1433

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May 16, 2019
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4 changes: 3 additions & 1 deletion manticore/native/cpu/aarch64.py
Original file line number Diff line number Diff line change
Expand Up @@ -1020,7 +1020,9 @@ def _ldr_str_immediate(cpu, reg_op, mem_op, mimm_op, ldr, size=None, sextend=Fal
if ldr:
result = cpu.read_int(base + imm, size)
if sextend:
result = Operators.SEXTEND(result, size, cpu.address_bit_size)
result = Operators.SEXTEND(result, size, reg_op.size)
else:
result = Operators.ZEXTEND(result, reg_op.size)
reg_op.write(result)
else:
reg = reg_op.read()
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23 changes: 23 additions & 0 deletions tests/native/test_aarch64cpu.py
Original file line number Diff line number Diff line change
Expand Up @@ -7593,6 +7593,29 @@ def test_ldrb_reg_sxtx0_32(self):
self.assertEqual(self.rf.read('X0'), 0x58)
self.assertEqual(self.rf.read('W0'), 0x58)

# LDRB misc.

# XXX: Add similar tests for other variants.
# XXX: Uses 'reset'.

@itest_setregs('X0=0x4142434445464749')
@itest_custom(
['strb w0, [sp]', 'ldrb w1, [sp]'],
multiple_insts=True
)
def test_strb_ldrb_imm_base32(self):
self.cpu.push_int(0x5152535455565758)
stack = self.cpu.STACK
self._execute()
self.assertEqual(self.cpu.read_int(stack), 0x5152535455565749)
self.assertEqual(self.rf.read('SP'), stack) # no writeback

stack = self.cpu.STACK
self._execute(reset=False)
self.assertEqual(self.rf.read('X1'), 0x49)
self.assertEqual(self.rf.read('W1'), 0x49)
self.assertEqual(self.rf.read('SP'), stack) # no writeback

# LDRH (immediate).

# ldrh w1, [x27] base register (opt. offset omitted): w1 = [x27]
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