core: added option/methods to enable/disable quad mode on SPI Flash

src/device.hpp

@@ -53,6 +53,9 @@ class Device {
 			printError("dump flash not supported"); return false;}
 		virtual bool protect_flash(uint32_t len) = 0;
 		virtual bool unprotect_flash() = 0;
+		virtual bool set_quad_bit(bool set_quad) {
+			(void)set_quad;
+			printError("Error: SPI Flash Quad mode configuration unsupported"); return false;}
 		virtual bool bulk_erase_flash() = 0;
 
 		virtual uint32_t idCode() = 0;

src/main.cpp

@@ -81,6 +81,8 @@ struct arguments {
 	string ip_adr;
 	uint32_t protect_flash;
 	bool unprotect_flash;
+	bool enable_quad;
+	bool disable_quad;
 	bool bulk_erase_flash;
 	string flash_sector;
 	bool skip_load_bridge;
@@ -123,7 +125,7 @@ int main(int argc, char **argv)
 			-1,            0,        "primary",   false,         -1,
 			/* vid, pid, index bus_addr, device_addr */
 				0,   0,   -1,     0,         0,
-			"127.0.0.1", 0, false, false, "", false, false,
+			"127.0.0.1", 0, false, false, false, false, "", false, false,
 			/* xvc server */
 			false, 3721, "-",
 			"", false, {},  // mcufw conmcu, user_misc_dev_list
@@ -636,6 +638,24 @@ int main(int argc, char **argv)
 		fpga->protect_flash(args.protect_flash);
 	}
 
+	/* Enable/disable SPI Flash quad mode */
+	if (args.enable_quad || args.disable_quad) {
+		bool ret = true;
+		if (args.enable_quad && args.disable_quad) {
+			printError("Error: can't set enable and disable Quad mode at same time");
+			ret = false;
+		} else  if (!fpga->set_quad_bit(args.enable_quad)) {
+			printError("Error: Failed to enable/disable Quad mode");
+			ret = false;
+		}
+
+		if (!ret) {
+			delete(fpga);
+			delete(jtag);
+			return EXIT_FAILURE;
+		}
+	}
+
 	/* detect/display flash */
 	if (args.detect_flash != 0) {
 		fpga->detect_flash();
@@ -769,6 +789,10 @@ int parse_opt(int argc, char **argv, struct arguments *args,
 			("dump-flash",  "Dump flash mode")
 			("bulk-erase",   "Bulk erase flash",
 				cxxopts::value<bool>(args->bulk_erase_flash))
+			("enable-quad",   "Enable quad mode for SPI Flash",
+				cxxopts::value<bool>(args->enable_quad))
+			("disable-quad",   "Disable quad mode for SPI Flash",
+				cxxopts::value<bool>(args->disable_quad))
 			("target-flash",
 				"for boards with multiple flash chips (some Xilinx UltraScale"
 				" boards), select the target flash: primary (default), secondary or both",

src/spiFlash.cpp

@@ -609,7 +609,7 @@ void SPIFlash::display_status_reg(uint8_t reg)
 		printf("BUSY : %d\n", (reg >> 7) & 0x01);
 	}
 
-	/* function register */
+	/* function and/or configuration register */
 	switch (dev_id) {
 		case 0x9d60:
 			_spi->spi_put(FLASH_RDFR, NULL, &reg, 1);
@@ -631,6 +631,20 @@ void SPIFlash::display_status_reg(uint8_t reg)
 			printf("BPNV   : %d\n", ((reg >> 3) & 0x01));
 			printf("TBPROT : %d\n", ((reg >> 5) & 0x01));
 			break;
+		case 0x20BA:
+			uint16_t nv_reg;
+			_spi->spi_put(FLASH_RDNVCR, NULL, (uint8_t*)&nv_reg, 2);
+			printf("\nNonvolatile Configuration Register\n");
+			printf("RDNVCR                   : %02x\n", nv_reg);
+			printf("Dummy Clock Cycles       : %d\n", ((nv_reg >> 12) & 0x0f));
+			printf("XIP mode at power-on/rst : %d\n", ((nv_reg >>  9) & 0x07));
+			printf("Output Driver strength   : %d\n", ((nv_reg >>  6) & 0x07));
+			/* 5: reserved */
+			printf("RST/HLD                  : %d\n", ((nv_reg >> 4) & 0x01));
+			printf("QUAD                     : %d\n", ((nv_reg >> 3) & 0x01));
+			printf("DUAL                     : %d\n", ((nv_reg >> 2) & 0x01));
+			/* 1:0: reserved */
+			break;
 	}
 }
 
@@ -867,65 +881,86 @@ int SPIFlash::enable_protection(uint32_t length)
 
 bool SPIFlash::set_quad_bit(bool set_quad)
 {
-	uint8_t reg_wr, reg_rd, reg_val, reg_val_verif;
+	uint8_t reg_wr, reg_rd; // read/write registers code
+	uint16_t reg_val;
+	uint32_t nb_rd_byte = 1; // Number of bytes to read (may differ from Flash models).
+	uint32_t nb_wr_byte = 1; // Number of bytes to write.
+	uint16_t quad_bit = 0; // quad_mask copy when bit must be set
 
 	if (!_flash_model) {
 		printError("spiFlash Error: can't configure Quad mode on unknown SPI Flash");
 		return false;
 	}
 
-	if (_flash_model->quad_offset == 0 || _flash_model->quad_register == NONER) {
+	if (_flash_model->quad_mask == 0 || _flash_model->quad_register == NONER) {
 		printError("spiFlash Error: SPI Flash has no Quad bit (or spiFlashdb must be updated)");
 		return false;
 	}
 
 	switch (_flash_model->quad_register) {
 		case STATR:
-			reg_wr = FLASH_WRSR;
 			reg_rd = FLASH_RDSR;
+			reg_wr = FLASH_WRSR;
+			break;
+		case NVCONFR:
+			reg_rd = FLASH_RDNVCR;
+			reg_wr = FLASH_WRNVCR;
+			nb_rd_byte = nb_wr_byte = 2;
 			break;
 		case CONFR:
-			reg_wr = FLASH_WRSR;
 			reg_rd = FLASH_RDCR;
+			reg_wr = FLASH_WRSR;
+			nb_wr_byte = 2;
 			break;
 		default:
 			printError("spiFlash Error: Unsupported register for Quad Enable bit configuration");
 			return false;
 	}
 
 	/* Read current register value */
-	_spi->spi_put(reg_rd, NULL, &reg_val, 1);
-	/* Only update Quad bit */
-	if (set_quad)
-		reg_val |= _flash_model->quad_offset;
-	else
-		reg_val &= ~_flash_model->quad_offset;
+	_spi->spi_put(reg_rd, NULL, (uint8_t *)&reg_val, nb_rd_byte);
+	reg_val &= ~_flash_model->quad_mask; // mask quad bit
+
+	/* Micron: enable 0, disable 1 */
+	if (_jedec_id == 0x20BA)
+		set_quad = ~set_quad;
+	if (set_quad) // set quad_bit when required
+		quad_bit = _flash_model->quad_mask;
+
+	/* update Quad bit */
+	reg_val |= quad_bit;
 
 	/* enable write access */
 	if (write_enable() != 0) {
 		printError("SPIFlash Error: failed to enable write");
 		return false;
 	}
 
-	/* Write register with the updated value */
-	if (_flash_model->quad_register == CONFR) {
-		uint8_t status = read_status_reg();
-		uint8_t write_val[2] = {status, reg_val};
-		_spi->spi_put(reg_wr, write_val, NULL, 2);
-	} else {
-		_spi->spi_put(reg_wr, &reg_val, NULL, 1);
+	/* Configuration register has no dedicated write instruction
+	 * -> a 16bits sequence must be sent to status register
+	 */
+	switch (_flash_model->quad_register) {
+		case CONFR:
+			uint8_t status = read_status_reg();
+			reg_val = ((reg_val & 0xff) << 8) | status;
+			_spi->spi_put(reg_wr, (uint8_t*) &reg_val, NULL, nb_wr_byte);
+			break;
 	}
 
-	/* disable write access (wait for completion) */
-	if (write_enable() != 0) {
-		printError("SPIFlash Error: failed to enable write");
+	/* Write register with the updated value */
+	_spi->spi_put(reg_wr, (uint8_t *)&reg_val, NULL, nb_wr_byte);
+
+	/* Wait for completion */
+	if (_spi->spi_wait(FLASH_RDSR, FLASH_RDSR_WEL, 0x00, 1000) != 0) {
+		printError("SPIFlash Error: failed to disable write");
 		return false;
 	}
 
-	/* Check if current value match written value */
-	_spi->spi_put(reg_rd, NULL, &reg_val_verif, 1);
+	/* Check if register is correctly updated */
+	_spi->spi_put(reg_rd, NULL, (uint8_t *)&reg_val, nb_rd_byte);
 
-	if ((reg_val_verif & _flash_model->quad_offset) == (reg_val & _flash_model->quad_offset)) {
+	if ((reg_val & _flash_model->quad_mask) == quad_bit) {
+		printf("%04x %04x %04x\n", reg_val, reg_val & _flash_model->quad_mask, quad_bit);
 		printError("SPIFlash Error: failed to update Quad bit");
 		return false;
 	}