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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,26 +1,22 @@ | ||
| <?xml version="1.0" ?> | ||
| <RadiantModule architecture="LIFCL" date="2023 11 06 08:19:22" device="LIFCL-33U" gen_platform="Radiant" generator="ipgen" library="ip" module="byte2pixel" name="b2p_2lane" package="FCCSP104" source_format="Verilog" speed="7_High-Performance_1.0V" vendor="latticesemi.com" version="1.6.0"> | ||
| <RadiantModule architecture="LIFCL" date="2024 02 14 16:50:14" device="LIFCL-33U" gen_platform="Radiant" generator="ipgen" library="ip" module="byte2pixel" name="b2p_2lane" package="FCCSP104" source_format="Verilog" speed="7_High-Performance_1.0V" vendor="latticesemi.com" version="1.6.1"> | ||
| <Package> | ||
| <File modified="2023 11 06 08:19:16" name="rtl/b2p_2lane_bb.v" type="black_box_verilog"/> | ||
| <File modified="2023 11 06 08:19:16" name="b2p_2lane.cfg" type="cfg"/> | ||
| <File modified="2023 11 06 08:19:16" name="misc/b2p_2lane_tmpl.v" type="template_verilog"/> | ||
| <File modified="2023 11 06 08:19:16" name="misc/b2p_2lane_tmpl.vhd" type="template_vhdl"/> | ||
| <File modified="2023 11 06 08:19:22" name="rtl/b2p_2lane.v" type="top_level_verilog"/> | ||
| <File modified="2023 11 06 08:19:22" name="constraints/b2p_2lane.ldc" type="timing_constraints"/> | ||
| <File modified="2023 11 06 08:19:22" name="testbench/dut_params.v" type="dependency_file"/> | ||
| <File modified="2023 11 06 08:19:22" name="testbench/dut_inst.v" type="dependency_file"/> | ||
| <File modified="2023 11 06 08:19:22" name="eval/dut_params.v" type="dependency_file"/> | ||
| <File modified="2023 11 06 08:19:22" name="eval/dut_inst.v" type="dependency_file"/> | ||
| <File modified="2023 11 06 08:19:22" name="component.xml" type="IP-XACT_component"/> | ||
| <File modified="2023 11 06 08:19:22" name="design.xml" type="IP-XACT_design"/> | ||
| <File modified="2022 12 03 04:43:29" name="testbench/byte_driver.v" type="testbench_verilog"/> | ||
| <File modified="2022 12 03 04:43:29" name="testbench/pixel_monitor.v" type="testbench_verilog"/> | ||
| <File modified="2022 12 03 04:43:29" name="testbench/tb_include/csi2_tasks.vh" type="testbench"/> | ||
| <File modified="2022 12 03 04:43:29" name="testbench/tb_include/dsi_tasks.vh" type="testbench"/> | ||
| <File modified="2022 12 03 04:43:29" name="testbench/tb_include/tb_params.vh" type="testbench"/> | ||
| <File modified="2022 12 03 04:43:29" name="testbench/tb_include/test_csi2_reset.vh" type="testbench"/> | ||
| <File modified="2022 12 03 04:43:29" name="testbench/tb_include/test_dsi_reset.vh" type="testbench"/> | ||
| <File modified="2022 12 03 04:43:29" name="testbench/tb_top.v" type="testbench_verilog"/> | ||
| <File modified="2022 12 03 04:43:29" name="eval/postsynconstraints.pdc" type="eval"/> | ||
| <File modified="2024 02 14 16:50:14" name="rtl/b2p_2lane_bb.v" type="black_box_verilog"/> | ||
| <File modified="2024 02 14 16:50:14" name="b2p_2lane.cfg" type="cfg"/> | ||
| <File modified="2024 02 14 16:50:14" name="misc/b2p_2lane_tmpl.v" type="template_verilog"/> | ||
| <File modified="2024 02 14 16:50:14" name="misc/b2p_2lane_tmpl.vhd" type="template_vhdl"/> | ||
| <File modified="2024 02 14 16:50:14" name="rtl/b2p_2lane.v" type="top_level_verilog"/> | ||
| <File modified="2024 02 14 16:50:14" name="constraints/b2p_2lane.ldc" type="timing_constraints"/> | ||
| <File modified="2024 02 14 16:50:14" name="testbench/dut_params.v" type="dependency_file"/> | ||
| <File modified="2024 02 14 16:50:14" name="testbench/dut_inst.v" type="dependency_file"/> | ||
| <File modified="2024 02 14 16:50:14" name="eval/dut_params.v" type="dependency_file"/> | ||
| <File modified="2024 02 14 16:50:14" name="eval/dut_inst.v" type="dependency_file"/> | ||
| <File modified="2024 02 14 16:50:14" name="component.xml" type="IP-XACT_component"/> | ||
| <File modified="2024 02 14 16:50:14" name="design.xml" type="IP-XACT_design"/> | ||
| <File modified="2023 12 01 08:42:35" name="testbench/byte_driver.v" type="testbench_verilog"/> | ||
| <File modified="2023 12 01 08:42:35" name="testbench/pixel_monitor.v" type="testbench_verilog"/> | ||
| <File modified="2023 12 01 08:42:35" name="testbench/tb_top.v" type="testbench_verilog"/> | ||
| <File modified="2024 02 15 00:50:14" name="eval/constraint.pdc" type="eval"/> | ||
| <File modified="2023 12 01 08:42:35" name="eval/ip_tmp_eval.pdc" type="eval"/> | ||
| </Package> | ||
| </RadiantModule> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,102 @@ | ||
| #------------------------------------------------------------------------------- | ||
| # Generated IP Settings | ||
| # LDC File: E:\Data\local_github\tinyCLUNX33_new\RTL\ip\b2p_2lane\constraints\b2p_2lane.ldc | ||
| #------------------------------------------------------------------------------- | ||
| set b2p_2lane_architecture "LIFCL" | ||
| set b2p_2lane_device "LIFCL-33U" | ||
| set b2p_2lane_package "FCCSP104" | ||
| set b2p_2lane_speed "7_High-Performance_1.0V" | ||
| set b2p_2lane_WRAPPER_INST "lscc_byte2pixel_inst" | ||
| set b2p_2lane_FAMILY "LIFCL" | ||
| set b2p_2lane_RX_TYPE "CSI-2" | ||
| set b2p_2lane_DSI_MODE "NONBURST_PULSES" | ||
| set b2p_2lane_NUM_RX_LANE 2 | ||
| set b2p_2lane_RX_GEAR 8 | ||
| set b2p_2lane_BYTE_CLK_FREQ 50.000000 | ||
| set b2p_2lane_AXI4_RX "OFF" | ||
| set b2p_2lane_NUM_TX_CH_INPUT 1 | ||
| set b2p_2lane_NUM_TX_CH 1 | ||
| set b2p_2lane_DT "6'h2B" | ||
| set b2p_2lane_PD_BUS_WIDTH 10 | ||
| set b2p_2lane_CTRL_POL "POSITIVE" | ||
| set b2p_2lane_VSA 5 | ||
| set b2p_2lane_HSA 8 | ||
| set b2p_2lane_SYNC_DELAY 5 | ||
| set b2p_2lane_SYNC_DELAY_CNTR_W 3 | ||
| set b2p_2lane_PIX_CLK_FREQ 100.000000 | ||
| set b2p_2lane_AXI4_TX "OFF" | ||
| set b2p_2lane_THRESHOLD 2 | ||
| set b2p_2lane_PIX_FIFO_DEPTH 8 | ||
| set b2p_2lane_PIX_FIFO_ADDR_WIDTH 3 | ||
| set b2p_2lane_FIFO_IMPL "EBR" | ||
| set b2p_2lane_WORD_CNT 5 | ||
| set b2p_2lane_DEBUG_EN 1 | ||
| set b2p_2lane_NUM_PIXELS 1 | ||
| set b2p_2lane_FRAMES_CNT 1 | ||
| set b2p_2lane_LINES_CNT 1 | ||
|
|
||
| #------------------------------------------------------------------------------- | ||
| # Evaluation Constraints | ||
| #------------------------------------------------------------------------------- | ||
| #------------------------------------------------------------------------------- | ||
| # GENERAL NOTES | ||
| # This post-synthesis constraint file is generated in LDC format and is | ||
| # compatible with Radiant SW. | ||
| # Note that "b2p_2lane" is a reserved keyword. This should be used as prefix of | ||
| # the variables used in the file. | ||
| #------------------------------------------------------------------------------- | ||
|
|
||
|
|
||
| #------------------------------------------------------------------------------- | ||
| # CLOCKS | ||
| #----- | ||
|
|
||
| set b2p_2lane_BYTECLK_PERIOD [expr {double(round(1000000/$b2p_2lane_BYTE_CLK_FREQ))/1000}] | ||
| set b2p_2lane_PIXELCLK_PERIOD [expr {double(round(1000000/$b2p_2lane_PIX_CLK_FREQ))/1000}] | ||
|
|
||
| if {$b2p_2lane_AXI4_RX=="ON"} { | ||
| create_clock -name {axis_sclk_i} -period $b2p_2lane_BYTECLK_PERIOD [get_ports axis_sclk_i] | ||
| } | ||
| if {$b2p_2lane_AXI4_RX=="OFF"} { | ||
| create_clock -name {clk_byte_i} -period $b2p_2lane_BYTECLK_PERIOD [get_ports clk_byte_i] | ||
| } | ||
| if {$b2p_2lane_AXI4_TX=="ON"} { | ||
| create_clock -name {axis_mclk_i} -period $b2p_2lane_PIXELCLK_PERIOD [get_ports axis_mclk_i] | ||
| } | ||
| if {$b2p_2lane_AXI4_TX=="OFF"} { | ||
| create_clock -name {clk_pixel_i} -period $b2p_2lane_PIXELCLK_PERIOD [get_ports clk_pixel_i] | ||
| } | ||
|
|
||
| # NOTE: The byte-to-pixel IP treats the byte clock and the pixel clock as | ||
| # asynchronous. | ||
| # Use "set_clock_groups -asynchronous" constraint only if the two | ||
| # clocks are asynchronous even for other logic outside the | ||
| # byte-to-pixel IP. | ||
| if {$b2p_2lane_AXI4_RX=="OFF"} { | ||
| if {$b2p_2lane_AXI4_TX=="OFF"} { | ||
| set_clock_groups -group [get_clocks clk_byte_i] -group [get_clocks clk_pixel_i] -asynchronous | ||
| } else { | ||
| set_clock_groups -group [get_clocks clk_byte_i] -group [get_clocks axis_mclk_i] -asynchronous | ||
| } | ||
| } else { | ||
| if {$b2p_2lane_AXI4_TX=="OFF"} { | ||
| set_clock_groups -group [get_clocks axis_sclk_i] -group [get_clocks clk_pixel_i] -asynchronous | ||
| } else { | ||
| set_clock_groups -group [get_clocks axis_sclk_i] -group [get_clocks axis_mclk_i] -asynchronous | ||
| } | ||
| } | ||
|
|
||
|
|
||
| #------------------------------------------------------------------------------- | ||
| # Timing Constraints | ||
| #----- | ||
|
|
||
| # multicycle path from wc_pix_sync* to pixcnt_c* and pix_out_cntr* # | ||
| set_multicycle_path -setup -from [get_pins -hierarchical {wc_pix_sync*/Q}] -to [get_nets -hierarchical {pix_out_cntr*}] 7 | ||
| set_multicycle_path -hold -from [get_pins -hierarchical {wc_pix_sync*/Q}] -to [get_nets -hierarchical {pix_out_cntr*}] 6 | ||
|
|
||
| # If using the encrypted IP, these CDC false_path constraints are not applied since it is within the encrypted block. ### | ||
| # Ignore these timing errors from the FIFO, or use set_clock_groups -asynchronous if there are no other logic | ||
| # outside the IP treating the pixel clock and the byteclock as synchronous. | ||
| #set_false_path -to [get_pins -hierarchical genblk*.rp_sync1_r*/DF] | ||
| #set_false_path -to [get_pins -hierarchical genblk*.wp_sync1_r*/DF] |
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