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Create a "self test" mode which checks things are working correctly #135

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mithro opened this issue Nov 13, 2015 · 1 comment
Open

Create a "self test" mode which checks things are working correctly #135

mithro opened this issue Nov 13, 2015 · 1 comment
Labels
boards-all firmware-cypress-fx2 firmware-fpga firmware-softcpu hdmi2usb level-firmware level-infrastructure level-software status-help-wanted type-enhancement
Milestone
Debugging Features

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@mithro
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mithro commented Nov 13, 2015

The "self test" mode should do the following;

  • Test that HDMI output is created correctly.
  • Test that HDMI input is sampled correctly.
  • Test that encoding is happening correctly.
  • Test that the USB streaming is happening correctly.

We probably need a bunch of "sample images" which test this.

One possibility is to have a "loop back" mode where you connect the HDMI input ports to the HDMI output ports. This would allow self testing but would make it hard to figure out where the problem actually is.

Having #130 - "Calculate CRC code on pixels during frame transfer" working would help make a lot of this easier.
@mithro
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mithro commented Nov 13, 2015

There will probably be some type of software on the computer needed to test the USB side of things.

@mithro mithro mentioned this issue Mar 23, 2016
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@mithro mithro modified the milestone: Debugging Features Mar 27, 2016
mithro added a commit that referenced this issue Oct 2, 2018
@mithro
Updating submodules.
9a878c1 
 * litedram changed from ea1ac4d to 5b02791
    * 5b02791 - modules: add tCCD to all modules <Florent Kermarrec>
    * 6c7a804 - Adding tCCD for DDR2 modules. <Tim 'mithro' Ansell>
    *   208f556 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
    |\
    | * 41a8a24 - modules: express tFAW in ns <Florent Kermarrec>
    | * 7062068 - modules: split DDR3 in 2 categories: Chips and SO-DIMMs <Florent Kermarrec>
    | * 0f46dc4 - modules: add DDR3-800 timings for MT41J128M16 and use it on arty example <Florent Kermarrec>
    | * 426ae23 - examples/litedram_gen: add sdram_module_speedgrade parameter <Florent Kermarrec>
    | * 1bc016c - test: add test_examples <Florent Kermarrec>
    | * f7f8169 - test: update downconverter/upconverter <Florent Kermarrec>
    | * 8de1d91 - core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) <Florent Kermarrec>
    * | 69eaf84 - Fix DDR2 and below compilation failure <>
    |/
    *   70516c4 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
    |\
    | * 5820970 - frontend/crossbar: fix #49 <Florent Kermarrec>
    * | 71f78d9 - Fix reordering controller rejecting all commands <>
    * | 8f14211 - Account for CWL in write to read timing <>
    |/
    * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec>
    *   06ca53d - Merge pull request #48 from enjoy-digital/staging <enjoy-digital>
    |\
    | *   5a4d063 - Merge branch 'master' into staging <enjoy-digital>
    | |\
    | |/
    |/|
    * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec>
    * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec>
    * |   869c8ee - Merge pull request #46 from enjoy-digital/WritePrechargeFix <enjoy-digital>
    |\ \
    | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <>
    * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec>
    |/ /
    * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec>
    * |   42ccf05 - Merge pull request #45 from enjoy-digital/tRAS_FIX <enjoy-digital>
    |\ \
    | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully>
    | * | 177d739 - Implement tRAS <John Sully>
    * | |   5902027 - Merge pull request #44 from enjoy-digital/tRC_Fix <enjoy-digital>
    |\ \ \
    | |/ /
    | * | 5f6b857 - This adds support for tRC timing parameters <John Sully>
    |/ /
    * |   1777720 - Merge pull request #42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital>
    |\ \
    | * | 06c8c2a - The actual fix <John Sully>
    | * | e22580f - remove unnecessary file <John Sully>
    | * | c028786 - Fix overflow bug from code review <John Sully>
    | * | 8447d69 - We wait an extra cycle for no reason <John Sully>
    |/ /
    | *   04aa04d - Merge pull request #43 from enjoy-digital/EfficencyFixes <enjoy-digital>
    | |\
    |/ /
    | * c4bd842 - Fix many bugs <John Sully>
    | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully>
    |/
    * c12404e - README: Add ECC <Florent Kermarrec>
    * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec>
    * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec>

 * liteeth changed from 3d86844 to 40b99ec
    * 40b99ec - test: use new RemoteClient import <Florent Kermarrec>
    * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec>

 * litepcie changed from 3e8de2d to a09d225
    * a09d225 - test: use new RemoteClient import <Florent Kermarrec>

 * litesata changed from fb72044 to b78a731
    * b78a731 - test: use new RemoteClient import <Florent Kermarrec>

 * litescope changed from 686db4f to 1634fa3
    * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec>
    * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec>

 * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-173-gd3b875b
    * d3b875b - Fixed on board green led pin number. Added "multi" led. <Piotr Esden-Tempski>
    * 56f359d - Added icebreaker platform. (#135) <Piotr Esden-Tempski>
    * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (#134) <hartytp>
    * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq>
    * 4621abc - sayma rtm: add clock mezzanine GPIO (#133) <hartytp>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 5b02791580db9d1bae64b6524b7aca3540d89937 litedram (remotes/origin/HEAD)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda)
 d3b875b46eee4d34e093e63cd769bdfaae0da3df migen (0.6.dev-173-gd3b875b)
mithro added a commit that referenced this issue Dec 18, 2018
@mithro
Updating submodules.
e723261 
 * edid-decode changed from 5eeb151 to 6def7bc
    * 6def7bc - edid-decode: make it easier to find the out-of-range monitor values <Hans Verkuil>

 * litedram changed from bc6a3f2 to 0572006
    * 0572006 - phy/kusddrphy: remove ResetSignal on ODELAYE3/ISERDESE3 that are dynamically adjusted, reduce sys latency <Florent Kermarrec>
    * 57ebcc5 - sdram_init/ddr4: enable dll <Florent Kermarrec>
    * 7a2ff33 - sdram_init/get_sdram_phy_py_header: generate mr1 value, fix init_sequence identation <Florent Kermarrec>
    * 33ff34b - core/refresher: use self.sync to fix build (verilog wire vs reg...) <Florent Kermarrec>
    * 8419f28 - core: split refresher, expose it and allow it to be reloaded externally. <Florent Kermarrec>
    * 8ec0bc6 - modules: improve the way we define DDR4 banks/groups <Florent Kermarrec>
    * 1618a76 - phy: add KUSDDRPHY to __init__.py <Florent Kermarrec>
    * d6350d9 - test/test_axi: reduce rand_level on writes <Florent Kermarrec>
    * 282b60e - frontend/axi: simplify LiteDRAMAXI2NativeW logic <Florent Kermarrec>
    * 6778c72 - test/test_axi: cleanup, all tests passings. <Florent Kermarrec>
    * ebb1d3c - frontend/axi/LiteDRAMAXI2NativeW: be sure that we already have the data before sending the command to the controller <Florent Kermarrec>
    * 0d5e554 - frontend/axi: expose aw_burst2beat/ar_burst2beat <Florent Kermarrec>
    * da65a80 - frontend/axi: expose w_buffer/r_buffer (can be useful for debug) <Florent Kermarrec>
    * 7f5d749 - test: add missing +x <Florent Kermarrec>
    * 7ef4869 - test/test_axi: also add randomness on rdata.valid and wdata.ready <Florent Kermarrec>
    * 3db68cd - test/test_axi/axi2native: add tests for each randomness parameters (ease finding regressions issues) <Florent Kermarrec>
    * 190b1bd - test/test_axi/axi2native: add finer control on randomness <Florent Kermarrec>
    * 4f137b9 - test/test_axi/axi2native: add random on len, just use writes as reads <Florent Kermarrec>
    * 2a799e4 - test/test_axi: set size on axi2native test <Florent Kermarrec>
    * e70d77e - phy/s7dddrphy: fix nphases = 2 (same code can be shared between nphases = 2 and nphases = 4) <Florent Kermarrec>
    * 170b3dc - frontend/wishbone: set aw/ar size on LiteDRAMWishbone2AXI <Florent Kermarrec>
    * 9a25506 - frontend/wishbone: fix wishbone.err on LiteDRAMWishbone2AXI <Florent Kermarrec>

 * litepcie changed from dddd3b1 to b29c3a0
    * b29c3a0 - README: update PHY description <Florent Kermarrec>
    * 07501b8 - core: expose depacketizer/packetizer/controller (useful for debug) <Florent Kermarrec>
    * bfd2813 - frontend/dma: remove 64KB DMA buffer size limitation by increasing length to 24 bits. <Florent Kermarrec>

 * litex changed from v0.1-620-gab799f7b to v0.1-664-g0ade06c0
    *   0ade06c0 - Merge pull request #138 from mithro/mainram-hack <Tim Ansell>
    |\
    | * 22d454ef - Hack to fix #136. <Tim 'mithro' Ansell>
    |/
    *   fa6fef1e - Merge pull request #135 from mithro/icestorm-ice40up5k <Tim Ansell>
    |\
    | * 9481781d - Add uwg30 package and up3k part. <Tim 'mithro' Ansell>
    * | e9f10492 - soc/cores/cpu/vexriscv: add add_debug method for debug variants <Florent Kermarrec>
    * | 35155e51 - soc/cores/cpu/vexriscv: add support for the new variants. <Florent Kermarrec>
    * | 2ace45e6 - soc/cores/cpu/vexriscv: update submodule <Florent Kermarrec>
    * | 6d6c2b4c - soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v) <Florent Kermarrec>
    * | 584fd51c - build/sim/verilator: add support for plaform.sources, some cleanup <Florent Kermarrec>
    * | c9915f89 - build/microsemi/libero_soc: fix typos <Florent Kermarrec>
    * | 99578bc6 - gen/sim/core: add args support on Display <Florent Kermarrec>
    * | fa260f5b - gen/fhdl: add simulation Display, Finish support. <Florent Kermarrec>
    * | 92a6169d - build/sim: add coverage parameter to enable code coverage <Florent Kermarrec>
    * | 0c687bc2 - soc/interconnect/stream: add support for buffered async fifo <Florent Kermarrec>
    * | bf3b4eec - gen: integrate migen changes <Florent Kermarrec>
    |/
    * 96527b5a - soc/interconnect/stream/gearbox: remove bit reversing by changing words order <Florent Kermarrec>
    *   1c8c2426 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   cc4ba656 - Merge pull request #130 from jfng/master <enjoy-digital>
    | |\
    | | * 71398e01 - litex_sim: add --trace argument <Jean-François Nguyen>
    * | | 8887fc24 - build/xilinx/vivado: disable xpm by default (can be enabled by passing enable_xpm=True to build). <Florent Kermarrec>
    |/ /
    * | ec46beeb - targets/ulx3s, versa_ecp5: use ECP5PLL <Florent Kermarrec>
    * | 18048eb4 - cores/clock: test and fix ECP5PLL, phase still not implemented. <Florent Kermarrec>
    * | 20dd95c5 - boards/platforms/ulx3s: add gpios 0-3 <Florent Kermarrec>
    |/
    * 909cff19 - bios/sdram: flush l2 cache only when present <Florent Kermarrec>
    * 2ad83778 - bios: allow testing main_ram at init when using an external controller <Florent Kermarrec>
    * cdfe0454 - build/microsemi/libero_soc: small cleanup <Florent Kermarrec>
    *   4592e323 - Merge pull request #128 from mithro/small-fix <enjoy-digital>
    |\
    | * 4f565c51 - stream.Endpoint: Pass extra arguments to superclass. <Tim 'mithro' Ansell>
    | * 3b9e4c4d - wishbone.SRAM: Support non-32bit wishbone widths. <Tim 'mithro' Ansell>
    * 515c0621 - cores/clock: add ECP5PLL <Florent Kermarrec>
    * 7623b5dd - soc/interconnect/stream/gearbox: inverse bit order <Florent Kermarrec>
    * d32e3930 - soc/cores/spi_flash: add missing endianness parameter <Florent Kermarrec>
    * c954943e - platforms/avalanche: add IOStandard on ddram pins <Florent Kermarrec>
    * 09a1cda9 - build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification <Florent Kermarrec>
    * a98e1ad6 - build/microsemi/libero_soc: add additional_timing_constraints <Florent Kermarrec>
    * b1668823 - build/microsemi/libero_soc: use die/package/speed from platform.device and add tcl_name helper <Florent Kermarrec>
    * 9df75d7d - platforms/avalanche: add package/speed to platform.device <Florent Kermarrec>
    * 953b1f70 - build/microsemi/libero_soc: remove previous impl directory if exists <Florent Kermarrec>
    * 18d513a1 - build/microsemi/libero_soc: give better names to pdc files: io/fp <Florent Kermarrec>
    * 4f092dbe - build/microsemi/libero_soc: add additional_constraints <Florent Kermarrec>
    * 206c9a46 - platforms/avalanche: fix ddram dq7 <Florent Kermarrec>
    * f0034077 - build/microsemi/libero_soc: add {} around port name. <Florent Kermarrec>
    * beeca856 - utils/litex_read_verilog: fix generated indent on instance <Florent Kermarrec>
    * 1fe7d09f - soc/integration/soc_core: add csr_map_update function <Florent Kermarrec>

 * migen changed from 0.6.dev-211-g022721a to 0.6.dev-228-g37db6bb
    * 37db6bb - Add uwg30 package and up3k part. <Tim 'mithro' Ansell>
    * abc2802 - fhdl/tracer: support Python 3.7 (#167) <Pierre-Olivier Vauboin>
    * e6ff283 - examples/sim: add display example <Florent Kermarrec>
    * 6742210 - sim/core: add Display support <Florent Kermarrec>
    * f46f014 - fhdl: add simulation Display, Finish support. <Florent Kermarrec>
    * 3d8a580 - build/lattice/icestorm: allow passing options to synth_ice40. <whitequark>
    * be608f9 - Revert "lattice/common: no need to differentiate nbits==1 and nbits > 1" <whitequark>
    * ac0dd18 - fhdl: give names to storage locations in MemoryToArray. <whitequark>
    * 01d9055 - fhdl: fix mismatch between _can_lower() and _lower_specials_step(). <whitequark>
    * f5005b5 - fhdl: append lowered specials to the original fragment. <whitequark>
    * 29b4e65 - genlib/resetsync: add __all__. <whitequark>
    * f0cd29f - genlib/fifo: add __all__. <whitequark>
    * c05fc0c - build/lattice/icestorm: add fine grained clock constraint support. <whitequark>
    * 0c57a44 - build/lattice/icestorm: simplify. <whitequark>
    * 4eca436 - fhdl/specials: allow passing name hint to TSTriple. <whitequark>
    * b5d723b - build/lattice/trellis: update for newer ecppack. <whitequark>
    * 3fc11b5 - build/lattice/icestorm: update package list for iCE40-HX8K. <Adam Greig>

Full submodule status
--
 6def7bc83dfb0338632e06a8b14c93faa6af8879 edid-decode (heads/master)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (heads/master)
 057200665f48fac184c46bbe6a82110f34ee01e4 litedram (heads/master)
 52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (heads/master)
 b29c3a07bc5e4e7eb8c12b174446b85371ffb3a0 litepcie (heads/master)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (heads/master)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (heads/master)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
 0993a4e0422454e522e1d2b491837034b8dcccbe litevideo (heads/master)
 0ade06c0f0b3ba747ceee5e35ea0abc7bc20df77 litex (v0.1-664-g0ade06c0)
 37db6bb52532b6d1c6bc8b724c2e8c6a38546c2a migen (0.6.dev-228-g37db6bb)
mithro added a commit that referenced this issue May 21, 2019
@mithro
Merge pull request #135 from antmicro/fix_zephyr_litex_board
345dfb6 
zephyr: Change LiteX+VexRiscv board name
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