mpfs_coremmc: clock and buswidth fixed

4bit bus width support and FIC0 clock is 125MHz
tiiuae · Feb 10, 2025 · 57c64a5 · 57c64a5
1 parent 8e01122
commit 57c64a5
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/arch/risc-v/src/mpfs/mpfs_coremmc.c b/arch/risc-v/src/mpfs/mpfs_coremmc.c
@@ -123,7 +123,7 @@
 
 /* Clocks and timing */
 
-#define MPFS_FPGA_FIC0_CLK                 (50000000)
+#define MPFS_FPGA_FIC0_CLK                 (125000000)
 
 #define COREMMC_BUSYTIMEOUT                (180)
 #define COREMMC_CMDTIMEOUT                 (100000)
@@ -1072,6 +1072,8 @@ static sdio_capset_t mpfs_capabilities(struct sdio_dev_s *dev)
       caps |= SDIO_CAPS_1BIT_ONLY;
     }
 
+  caps |= SDIO_CAPS_4BIT;
+
   return caps;
 }