Pass all of the instruction tests

thesecretclub · Jan 14, 2024 · cc6e883 · cc6e883
1 parent a70b6cd
commit cc6e883
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Showing 5 changed files with 151 additions and 106 deletions.
diff --git a/riscvm/opcodes.h b/riscvm/opcodes.h
@@ -62,7 +62,7 @@ enum RV64_Imm64
     rv64_imm64_slti = 0b00010,
     rv64_imm64_sltiu = 0b00011,
     rv64_imm64_xori = 0b00100,
-    rv64_imm64_srli = 0b00101,
+    rv64_imm64_srxi = 0b00101, // srli/srai
     rv64_imm64_ori = 0b00110,
     rv64_imm64_andi = 0b00111,
 };
@@ -71,7 +71,7 @@ enum RV64_Imm32
 {
     rv64_imm32_addiw = 0b00000,
     rv64_imm32_slliw = 0b00001,
-    rv64_imm32_srliw = 0b00101,
+    rv64_imm32_srxiw = 0b00101, // srliw/sraiw
 };
 
 enum RV64_Load

diff --git a/riscvm/opcodes.json b/riscvm/opcodes.json
@@ -59,15 +59,15 @@
     "rv64_imm32": {
         "0": "addiw",
         "1": "slliw",
-        "5": "srliw"
+        "5": "srxiw"
     },
     "rv64_imm64": {
         "0": "addi",
         "1": "slli",
         "2": "slti",
         "3": "sltiu",
         "4": "xori",
-        "5": "srli",
+        "5": "srxi",
         "6": "ori",
         "7": "andi"
     },

diff --git a/riscvm/riscvm.cpp b/riscvm/riscvm.cpp
@@ -293,58 +293,6 @@ ALWAYS_INLINE static bool riscvm_handle_syscall(riscvm_ptr self, uint64_t code,
     return true;
 }
 
-ALWAYS_INLINE static int64_t riscvm_shl_int64(int64_t a, int64_t b)
-{
-    if (LIKELY(b >= 0 && b < 64))
-    {
-        return ((uint64_t)a) << b;
-    }
-    else if (UNLIKELY(b < 0 && b > -64))
-    {
-        return (uint64_t)a >> -b;
-    }
-    else
-    {
-        return 0;
-    }
-}
-
-ALWAYS_INLINE static int64_t riscvm_shr_int64(int64_t a, int64_t b)
-{
-    if (LIKELY(b >= 0 && b < 64))
-    {
-        return (uint64_t)a >> b;
-    }
-    else if (UNLIKELY(b < 0 && b > -64))
-    {
-        return (uint64_t)a << -b;
-    }
-    else
-    {
-        return 0;
-    }
-}
-
-ALWAYS_INLINE static int64_t riscvm_asr_int64(int64_t a, int64_t b)
-{
-    if (LIKELY(b >= 0 && b < 64))
-    {
-        return a >> b;
-    }
-    else if (UNLIKELY(b >= 64))
-    {
-        return a < 0 ? -1 : 0;
-    }
-    else if (UNLIKELY(b < 0 && b > -64))
-    {
-        return a << -b;
-    }
-    else
-    {
-        return 0;
-    }
-}
-
 ALWAYS_INLINE static __int128 riscvm_shr_int128(__int128 a, __int128 b)
 {
     if (LIKELY(b >= 0 && b < 128))
@@ -539,7 +487,7 @@ ALWAYS_INLINE static bool handler_rv64_imm64(riscvm_ptr self, Instruction inst)
     }
     case rv64_imm64_slli:
     {
-        val = riscvm_shl_int64(val, inst.rwtype.rs2);
+        val = val << (inst.itype.imm & 0b111111);
         break;
     }
     case rv64_imm64_slti:
@@ -571,15 +519,17 @@ ALWAYS_INLINE static bool handler_rv64_imm64(riscvm_ptr self, Instruction inst)
         val = val ^ imm;
         break;
     }
-    case rv64_imm64_srli:
+    case rv64_imm64_srxi:
     {
-        if (inst.rwtype.shamt)
+        if ((inst.itype.imm >> 10) & 1)
         {
-            val = riscvm_asr_int64(val, inst.rwtype.rs2);
+            // srai
+            val = val >> (imm & 0b111111);
         }
         else
         {
-            val = riscvm_shr_int64(val, inst.rwtype.rs2);
+            // srli
+            val = (uint64_t)val >> (imm & 0b111111);
         }
         break;
     }
@@ -619,18 +569,20 @@ ALWAYS_INLINE static bool handler_rv64_imm32(riscvm_ptr self, Instruction inst)
     }
     case rv64_imm32_slliw:
     {
-        val = (int64_t)(int32_t)riscvm_shl_int64(val, imm);
+        val = int32_t(val) << (imm & 0b11111);
         break;
     }
-    case rv64_imm32_srliw:
+    case rv64_imm32_srxiw:
     {
-        if (inst.rwtype.shamt)
+        if ((inst.itype.imm >> 10) & 1)
         {
-            val = (int64_t)(int32_t)riscvm_asr_int64(val, inst.rwtype.rs2);
+            // sraiw
+            val = int32_t(val) >> (imm & 0b11111);
         }
         else
         {
-            val = (int64_t)(int32_t)riscvm_shr_int64(val, inst.rwtype.rs2);
+            // srliw
+            val = int32_t(uint32_t(val) >> (imm & 0b11111));
         }
         break;
     }
@@ -666,7 +618,7 @@ ALWAYS_INLINE static bool handler_rv64_op64(riscvm_ptr self, Instruction inst)
     }
     case rv64_op64_sll:
     {
-        val = riscvm_shl_int64(val1, val2 & 0x1f);
+        val = val1 << (val2 & 0b111111);
         break;
     }
     case rv64_op64_slt:
@@ -700,12 +652,12 @@ ALWAYS_INLINE static bool handler_rv64_op64(riscvm_ptr self, Instruction inst)
     }
     case rv64_op64_srl:
     {
-        val = riscvm_shr_int64(val1, val2 & 0x1f);
+        val = (uint64_t)val1 >> (val2 & 0b11111);
         break;
     }
     case rv64_op64_sra:
     {
-        val = riscvm_asr_int64(val1, val2 & 0x1f);
+        val = val1 >> (val2 & 0b11111);
         break;
     }
     case rv64_op64_or:
@@ -829,12 +781,12 @@ ALWAYS_INLINE static bool handler_rv64_op32(riscvm_ptr self, Instruction inst)
     }
     case rv64_op32_sllw:
     {
-        val = (int64_t)(int32_t)riscvm_shl_int64(val1, (val2 & 0x1f));
+        val = int32_t(val1 << (val2 & 0b11111));
         break;
     }
     case rv64_op32_srlw:
     {
-        val = (int64_t)(int32_t)riscvm_shr_int64(val1, (val2 & 0x1f));
+        val = int32_t(uint32_t(val1) >> (val2 & 0b11111));
         break;
     }
     case rv64_op32_mulw:
@@ -908,7 +860,7 @@ ALWAYS_INLINE static bool handler_rv64_op32(riscvm_ptr self, Instruction inst)
     }
     case rv64_op32_sraw:
     {
-        val = (int64_t)(int32_t)riscvm_asr_int64(val1, val2 & 0x1f);
+        val = int32_t(val1) >> (val2 & 0b11111);
         break;
     }
     case rv64_op32_subw:

diff --git a/riscvm/shuffled_opcodes.h b/riscvm/shuffled_opcodes.h
@@ -67,13 +67,13 @@ enum RV64_Imm64
     rv64_imm64_andi = 0b00100, // original 0b00111
     rv64_imm64_sltiu = 0b00101, // original 0b00011
     rv64_imm64_addi = 0b00110, // original 0b00000
-    rv64_imm64_srli = 0b00111, // original 0b00101
+    rv64_imm64_srxi = 0b00111, // original 0b00101
     rv64_imm64_invalid = 0b11111, // placeholder
 };
 
 enum RV64_Imm32
 {
-    rv64_imm32_srliw = 0b00000, // original 0b00101
+    rv64_imm32_srxiw = 0b00000, // original 0b00101
     rv64_imm32_slliw = 0b00001, // original 0b00001
     rv64_imm32_addiw = 0b00010, // original 0b00000
     rv64_imm32_invalid = 0b11111, // placeholder