Merge branch 'ReAlUA-master'

thanks4opensource · Dec 31, 2020 · 65a282a · 65a282a
2 parents 6e3f0dd + 607b221
commit 65a282a
Show file tree

Hide file tree

Showing 3 changed files with 22 additions and 13 deletions.
diff --git a/.gitignore b/.gitignore
@@ -1,2 +1,5 @@
 # Compiled Object files
 *.o
+
+# Experimental development
+RCS
diff --git a/Makefile b/Makefile
@@ -0,0 +1,2 @@
+README.html: README.md
+	multimarkdown -o $@ $<
diff --git a/build/buck50.py b/build/buck50.py
@@ -1,3 +1,5 @@
+#!/usr/bin/env python3
+
 # buck50: Test and measurement firmware for “Blue Pill” STM32F103 development board
 # Copyright (C) 2019,2020 Mark R. Rubin aka "thanks4opensource"
 #
@@ -4262,18 +4264,17 @@ def upload_analog(samples     ,
                   filename    ):
     # recompute each time because MCU_HZ might
     #   have been changet by configure['adjust'] action
-    # unknown why off by factor of 2
-    #   seems consistent across sample/hold/adc times
-    FUDGE = 0.5
+    # firmware uses ADCPRE_DIV_6
+    ADCCLK_HZ = CPU_HZ / 6.0
     SAMPLE_MICROSECONDS = {
-        AdcSampHold.T_1_5   : FUDGE * (1.5   + 12.5) * 12 / CPU_HZ,
-        AdcSampHold.T_7_5   : FUDGE * (7.5   + 12.5) * 12 / CPU_HZ,
-        AdcSampHold.T_13_5  : FUDGE * (13.5  + 12.5) * 12 / CPU_HZ,
-        AdcSampHold.T_28_5  : FUDGE * (28.5  + 12.5) * 12 / CPU_HZ,
-        AdcSampHold.T_41_5  : FUDGE * (41.5  + 12.5) * 12 / CPU_HZ,
-        AdcSampHold.T_55_5  : FUDGE * (55.5  + 12.5) * 12 / CPU_HZ,
-        AdcSampHold.T_71_5  : FUDGE * (71.5  + 12.5) * 12 / CPU_HZ,
-        AdcSampHold.T_239_5 : FUDGE * (239.5 + 12.5) * 12 / CPU_HZ,
+        AdcSampHold.T_1_5   : (1.5   + 12.5) / ADCCLK_HZ,
+        AdcSampHold.T_7_5   : (7.5   + 12.5) / ADCCLK_HZ,
+        AdcSampHold.T_13_5  : (13.5  + 12.5) / ADCCLK_HZ,
+        AdcSampHold.T_28_5  : (28.5  + 12.5) / ADCCLK_HZ,
+        AdcSampHold.T_41_5  : (41.5  + 12.5) / ADCCLK_HZ,
+        AdcSampHold.T_55_5  : (55.5  + 12.5) / ADCCLK_HZ,
+        AdcSampHold.T_71_5  : (71.5  + 12.5) / ADCCLK_HZ,
+        AdcSampHold.T_239_5 : (239.5 + 12.5) / ADCCLK_HZ,
     }
 
     trig_chan_name = adc_configs[channel_ndxs & 0x0f]['name'].val
@@ -4328,7 +4329,7 @@ def upload_analog(samples     ,
                     trig_chan_name,
                     trgr_printf   )
         if file:
-            file.write("time,%s" % trig_chan_name)
+            file.write("time,%s\n" % trig_chan_name)
     else: # two channels
         printf =   "%%4d   %s    %s %s   %s %s\n"   \
                  % (time_printf   ,
@@ -4366,7 +4367,10 @@ def upload_analog(samples     ,
                                  ranged_2  )
         if file:
             if num_channels == 1:
-                file.write("%g,%g\n" % (num * tick, ranged_1))
+                file.write("%g,%g\n%g,%g\n" % ( num * tick     ,
+                                                ranged_1       ,
+                                               (num + 1) * tick,
+                                                ranged_2)      )
             else:
                 file.write("%g,%g,%g\n" % (num * tick, ranged_1, ranged_2))
         else: