SIMD: implements v128 load, store and lane manipulations.

internal/asm/amd64/assembler.go

@@ -28,6 +28,18 @@ type Assembler interface {
 		dstReg asm.Register,
 	)
 
+	// CompileMemoryWithIndexAndArgToRegister is the same as CompileMemoryWithIndexToRegister except that this
+	// also accepts one argument.
+	CompileMemoryWithIndexAndArgToRegister(
+		instruction asm.Instruction,
+		srcBaseReg asm.Register,
+		srcOffsetConst int64,
+		srcIndex asm.Register,
+		srcScale int16,
+		dstReg asm.Register,
+		arg byte,
+	)
+
 	// CompileRegisterToMemoryWithIndex adds an instruction where source operand is the register `SrcReg`,
 	// and the destination is the memory address specified as `dstBaseReg + dstOffsetConst + dstIndex*dstScale`
 	// Note: dstScale must be one of 1, 2, 4, 8.
@@ -40,6 +52,18 @@ type Assembler interface {
 		dstScale int16,
 	)
 
+	// CompileRegisterToMemoryWithIndexAndArg is the same as CompileRegisterToMemoryWithIndex except that this
+	// also accepts one argument.
+	CompileRegisterToMemoryWithIndexAndArg(
+		instruction asm.Instruction,
+		srcReg asm.Register,
+		dstBaseReg asm.Register,
+		dstOffsetConst int64,
+		dstIndex asm.Register,
+		dstScale int16,
+		arg byte,
+	)
+
 	// CompileRegisterToConst adds an instruction where source operand is the register `srcRegister`,
 	// and the destination is the const `value`.
 	CompileRegisterToConst(instruction asm.Instruction, srcRegister asm.Register, value int64) asm.Node
@@ -57,15 +81,14 @@ type Assembler interface {
 	CompileNoneToMemory(instruction asm.Instruction, baseReg asm.Register, offset int64)
 
 	// CompileConstToMemory adds an instruction where source operand is the constant `value` and
-	// the destination is the memory address specified as `dstbaseReg+dstOffset`.
-	CompileConstToMemory(instruction asm.Instruction, value int64, dstbaseReg asm.Register, dstOffset int64) asm.Node
+	// the destination is the memory address specified as `dstBaseReg+dstOffset`.
+	CompileConstToMemory(instruction asm.Instruction, value int64, dstBaseReg asm.Register, dstOffset int64) asm.Node
 
 	// CompileMemoryToConst adds an instruction where source operand is the memory address, and
 	// the destination is the constant `value`.
 	CompileMemoryToConst(instruction asm.Instruction, srcBaseReg asm.Register, srcOffset int64, value int64) asm.Node
-}
 
-// Mode represents a Mode for specific instruction.
-// For example, ROUND** instructions' behavior can be modified "Mode" constant.
-// See https://www.felixcloutier.com/x86/roundss for ROUNDSS as an example.
-type Mode = byte
+	// CompileLoadStaticConstToRegister adds an instruction where the source operand is asm.StaticConst located in the
+	// memory and the destination is the dstReg.
+	CompileLoadStaticConstToRegister(instruction asm.Instruction, c asm.StaticConst, dstReg asm.Register) error
+}

internal/asm/amd64/consts.go

@@ -175,11 +175,11 @@ const (
 	MOVW
 	// MOVWLSX is the MOVSX instruction for a word in 32-bit mode. https://www.felixcloutier.com/x86/movsx:movsxd
 	MOVWLSX
-	// MOVWLZX is the MOVZX instruction for a word in 32-bit mode. https://www.felixcloutier.com/x86/movsx:movsxd
+	// MOVWLZX is the MOVZX instruction for a word in 32-bit mode. https://www.felixcloutier.com/x86/movzx
 	MOVWLZX
 	// MOVWQSX is the MOVSX instruction for a word in 64-bit mode. https://www.felixcloutier.com/x86/movsx:movsxd
 	MOVWQSX
-	// MOVWQZX is the MOVZX instruction for a word in 64-bit mode. https://www.felixcloutier.com/x86/movsx:movsxd
+	// MOVWQZX is the MOVZX instruction for a word in 64-bit mode. https://www.felixcloutier.com/x86/movzx
 	MOVWQZX
 	// MULL is the MUL instruction in 32-bit mode. https://www.felixcloutier.com/x86/mul
 	MULL
@@ -303,9 +303,17 @@ const (
 	NOP
 	// UD2 is the UD2 instruction. https://www.felixcloutier.com/x86/ud
 	UD2
-	// MOVDQU is the MOVDQU instruction. https://www.felixcloutier.com/x86/movdqu:vmovdqu8:vmovdqu16:vmovdqu32:vmovdqu64
+	// MOVDQU is the MOVDQU instruction in 64-bit mode. https://www.felixcloutier.com/x86/movdqu:vmovdqu8:vmovdqu16:vmovdqu32:vmovdqu64
 	MOVDQU
-	// PINSRQ is the PINSQR instruction. https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq
+	// MOVDQA is the MOVDQA instruction in 64-bit mode. https://www.felixcloutier.com/x86/movdqa:vmovdqa32:vmovdqa64
+	MOVDQA
+	// PINSRB is the PINSRB instruction. https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq
+	PINSRB
+	// PINSRW is the PINSRW instruction. https://www.felixcloutier.com/x86/pinsrw
+	PINSRW
+	// PINSRD is the PINSRD instruction. https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq
+	PINSRD
+	// PINSRQ is the PINSRQ instruction. https://www.felixcloutier.com/x86/pinsrb:pinsrd:pinsrq
 	PINSRQ
 	// PADDB is the PADDB instruction. https://www.felixcloutier.com/x86/paddb:paddw:paddd:paddq
 	PADDB
@@ -315,10 +323,66 @@ const (
 	PADDL
 	// PADDQ is the PADDQ instruction. https://www.felixcloutier.com/x86/paddb:paddw:paddd:paddq
 	PADDQ
+	// PSUBB is the PSUBB instruction. https://www.felixcloutier.com/x86/psubb:psubw:psubd
+	PSUBB
+	// PSUBW is the PSUBW instruction. https://www.felixcloutier.com/x86/psubb:psubw:psubd
+	PSUBW
+	// PSUBL is the PSUBD instruction. https://www.felixcloutier.com/x86/psubb:psubw:psubd
+	PSUBL
+	// PSUBQ is the PSUBQ instruction. https://www.felixcloutier.com/x86/psubq
+	PSUBQ
 	// ADDPS is the ADDPS instruction. https://www.felixcloutier.com/x86/addps
 	ADDPS
 	// ADDPD is the ADDPD instruction. https://www.felixcloutier.com/x86/addpd
 	ADDPD
+	// SUBPS is the SUBPS instruction. https://www.felixcloutier.com/x86/subps
+	SUBPS
+	// SUBPD is the SUBPD instruction. https://www.felixcloutier.com/x86/subpd
+	SUBPD
+	// PMOVSXBW is the PMOVSXBW instruction https://www.felixcloutier.com/x86/pmovsx
+	PMOVSXBW
+	// PMOVSXWD is the PMOVSXWD instruction https://www.felixcloutier.com/x86/pmovsx
+	PMOVSXWD
+	// PMOVSXDQ is the PMOVSXDQ instruction https://www.felixcloutier.com/x86/pmovsx
+	PMOVSXDQ
+	// PMOVZXBW is the PMOVZXBW instruction https://www.felixcloutier.com/x86/pmovzx
+	PMOVZXBW
+	// PMOVZXWD is the PMOVZXWD instruction https://www.felixcloutier.com/x86/pmovzx
+	PMOVZXWD
+	// PMOVZXDQ is the PMOVZXDQ instruction https://www.felixcloutier.com/x86/pmovzx
+	PMOVZXDQ
+	// PSHUFB is the PSHUFB instruction https://www.felixcloutier.com/x86/pshufb
+	PSHUFB
+	// PSHUFD is the PSHUFD instruction https://www.felixcloutier.com/x86/pshufd
+	PSHUFD
+	// PXOR is the PXOR instruction https://www.felixcloutier.com/x86/pxor
+	PXOR
+	// PEXTRB is the PEXTRB instruction https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq
+	PEXTRB
+	// PEXTRW is the PEXTRW instruction https://www.felixcloutier.com/x86/pextrw
+	PEXTRW
+	// PEXTRD is the PEXTRD instruction https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq
+	PEXTRD
+	// PEXTRQ is the PEXTRQ instruction https://www.felixcloutier.com/x86/pextrb:pextrd:pextrq
+	PEXTRQ
+	// MOVLHPS is the MOVLHPS instruction https://www.felixcloutier.com/x86/movlhps
+	MOVLHPS
+	// INSERTPS is the INSERTPS instruction https://www.felixcloutier.com/x86/insertps
+	INSERTPS
+	// PTEST is the PTEST instruction https://www.felixcloutier.com/x86/ptest
+	PTEST
+	// PCMPEQB is the PCMPEQB instruction https://www.felixcloutier.com/x86/pcmpeqb:pcmpeqw:pcmpeqd
+	PCMPEQB
+	// PCMPEQW is the PCMPEQW instruction https://www.felixcloutier.com/x86/pcmpeqb:pcmpeqw:pcmpeqd
+	PCMPEQW
+	// PCMPEQD is the PCMPEQD instruction https://www.felixcloutier.com/x86/pcmpeqb:pcmpeqw:pcmpeqd
+	PCMPEQD
+	// PCMPEQQ is the PCMPEQQ instruction https://www.felixcloutier.com/x86/pcmpeqq
+	PCMPEQQ
+	// PADDUSB is the PADDUSB instruction https://www.felixcloutier.com/x86/paddusb:paddusw
+	PADDUSB
+	// MOVSD is the MOVSD instruction https://www.felixcloutier.com/x86/movsd
+	MOVSD
 )
 
 // InstructionName returns the name for an instruction
@@ -586,6 +650,12 @@ func InstructionName(instruction asm.Instruction) string {
 		return "UD2"
 	case MOVDQU:
 		return "MOVDQU"
+	case PINSRB:
+		return "PINSRB"
+	case PINSRW:
+		return "PINSRW"
+	case PINSRD:
+		return "PINSRD"
 	case PINSRQ:
 		return "PINSRQ"
 	case PADDB:
@@ -600,6 +670,64 @@ func InstructionName(instruction asm.Instruction) string {
 		return "ADDPS"
 	case ADDPD:
 		return "ADDPD"
+	case PSUBB:
+		return "PSUBB"
+	case PSUBW:
+		return "PSUBW"
+	case PSUBL:
+		return "PSUBL"
+	case PSUBQ:
+		return "PSUBQ"
+	case SUBPS:
+		return "SUBPS"
+	case SUBPD:
+		return "SUBPD"
+	case PMOVSXBW:
+		return "PMOVSXBW"
+	case PMOVSXWD:
+		return "PMOVSXWD"
+	case PMOVSXDQ:
+		return "PMOVSXDQ"
+	case PMOVZXBW:
+		return "PMOVZXBW"
+	case PMOVZXWD:
+		return "PMOVZXWD"
+	case PMOVZXDQ:
+		return "PMOVZXDQ"
+	case PSHUFB:
+		return "PSHUFB"
+	case PSHUFD:
+		return "PSHUFD"
+	case PXOR:
+		return "PXOR"
+	case PEXTRB:
+		return "PEXTRB"
+	case PEXTRW:
+		return "PEXTRW"
+	case PEXTRD:
+		return "PEXTRD"
+	case PEXTRQ:
+		return "PEXTRQ"
+	case INSERTPS:
+		return "INSERTPS"
+	case MOVLHPS:
+		return "MOVLHPS"
+	case PTEST:
+		return "PTEST"
+	case PCMPEQB:
+		return "PCMPEQB"
+	case PCMPEQW:
+		return "PCMPEQW"
+	case PCMPEQD:
+		return "PCMPEQD"
+	case PCMPEQQ:
+		return "PCMPEQQ"
+	case PADDUSB:
+		return "PADDUSB"
+	case MOVDQA:
+		return "MOVDQA"
+	case MOVSD:
+		return "MOVSD"
 	}
 	return "Unknown"
 }