wip

Signed-off-by: Takeshi Yoneda <[email protected]>

internal/asm/arm64/assembler.go

@@ -67,27 +67,35 @@ type Assembler interface {
 	// otherwise set 0.
 	CompileConditionalRegisterSet(cond asm.ConditionalRegisterState, dstReg asm.Register)
 
-	// CompileMemoryToVectorRegister TODO
+	// CompileMemoryToVectorRegister adds an instruction where source operands is the memory address specified by `sourceBaseReg+sourceOffsetConst`
+	// and the destination is `destinationReg` vector register.
 	CompileMemoryToVectorRegister(instruction asm.Instruction, srcBaseReg asm.Register, srcOffset asm.ConstantValue, dstReg asm.Register, arrangement VectorArrangement)
 
-	// CompileMemoryWithRegisterOffsetToVectorRegister TODO
+	// CompileMemoryWithRegisterOffsetToVectorRegister is the same as CompileMemoryToVectorRegister except that the offset is specified by the `srcOffsetRegister` register.
 	CompileMemoryWithRegisterOffsetToVectorRegister(instruction asm.Instruction, srcBaseReg, srcOffsetRegister asm.Register, dstReg asm.Register, arrangement VectorArrangement)
 
-	// CompileVectorRegisterToMemory TODO
+	// CompileVectorRegisterToMemory adds an instruction where source operand is `sourceRegister` vector register and the destination is the
+	// memory address specified by `destinationBaseRegister+destinationOffsetConst`.
 	CompileVectorRegisterToMemory(instruction asm.Instruction, srcReg, dstBaseReg asm.Register, dstOffset asm.ConstantValue, arrangement VectorArrangement)
 
-	// CompileVectorRegisterToMemoryWithRegisterOffset TODO
+	// CompileVectorRegisterToMemoryWithRegisterOffset is the same as CompileVectorRegisterToMemory except that the offset is specified by the `dstOffsetRegister` register.
 	CompileVectorRegisterToMemoryWithRegisterOffset(instruction asm.Instruction, srcReg, dstBaseReg, dstOffsetRegister asm.Register, arrangement VectorArrangement)
 
-	// CompileRegisterToVectorRegister TODO
+	// CompileRegisterToVectorRegister adds an instruction where source operand is `sourceRegister` general purpose register
+	// and the destination is the `dstReg` vector register. The destination vector's arrangement and index of element can be
+	// given by `arrangement` and `index`, but not all the instructions will use them.
 	CompileRegisterToVectorRegister(instruction asm.Instruction, srcReg, dstReg asm.Register,
 		arrangement VectorArrangement, index VectorIndex)
 
-	// CompileVectorRegisterToRegister TODO
+	// CompileVectorRegisterToRegister adds an instruction where destination operand is `dstReg` general purpose register
+	// and the source is the `srcReg` vector register. The source vector's arrangement and index of element can be
+	// given by `arrangement` and `index`, but not all the instructions will use them.
 	CompileVectorRegisterToRegister(instruction asm.Instruction, srcReg, dstReg asm.Register,
 		arrangement VectorArrangement, index VectorIndex)
 
-	// CompileVectorRegisterToVectorRegister TODO
+	// CompileVectorRegisterToVectorRegister adds an instruction where both source and destination operands are vector registers.
+	// The vector's arrangement can be specified `arrangement`, and the source and destination element's index are given by
+	// `srcIndex` and `dstIndex` respectively, but not all the instructions will use them.
 	CompileVectorRegisterToVectorRegister(instruction asm.Instruction, srcReg, dstReg asm.Register, arrangement VectorArrangement, srcIndex, dstIndex VectorIndex)
 
 	// CompileVectorRegisterToVectorRegisterWithConst TODO

internal/asm/arm64/consts.go

@@ -673,11 +673,9 @@ const (
 	UCVTFWS
 	// UDIV is the UDIV instruction .https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV
 	UDIV
-	// UDVIW is the UDIV instruction, in 64-bit mode.https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV
+	// UDIVW is the UDIV instruction, in 64-bit mode.https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV
 	UDIVW
 
-	// Vector instructions.
-
 	// VBIT is the BIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/BIT--vector-
 	VBIT
 	// VCNT is the CNT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/CNT--vector-
@@ -723,9 +721,9 @@ const (
 	CMEQ
 	// ADDP is the ADDP instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/ADDP--vector-
 	ADDP
-	// TBL1 is the TBL instruction whose source is one vector. // https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup-
+	// TBL1 is the TBL instruction whose source is one vector. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup-
 	TBL1
-	// TBL2 is the TBL instruction whose source is two vectors. // https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup-
+	// TBL2 is the TBL instruction whose source is two vectors. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup-
 	TBL2
 )
 

internal/engine/compiler/compiler.go

@@ -413,15 +413,36 @@ type compiler interface {
 	// compileV128Sub adds instruction to subtract two vector values whose shape is specified as `o.Shape`.
 	// See wasm.OpcodeVecI8x16Sub wasm.OpcodeVecI16x8Sub wasm.OpcodeVecI32x4Sub wasm.OpcodeVecI64x2Sub wasm.OpcodeVecF32x4Sub wasm.OpcodeVecF64x2Sub
 	compileV128Sub(o *wazeroir.OperationV128Sub) error
+	// compileV128Load adds instruction to perform vector load kind instructions.
+	// See wasm.OpcodeVecV128Load* instructions.
 	compileV128Load(o *wazeroir.OperationV128Load) error
+	// compileV128LoadLane adds instructions which are equivalent to wasm.OpcodeVecV128LoadXXLane instructions.
+	// See wasm.OpcodeVecV128Load8LaneName wasm.OpcodeVecV128Load16LaneName wasm.OpcodeVecV128Load32LaneName wasm.OpcodeVecV128Load64LaneName
 	compileV128LoadLane(o *wazeroir.OperationV128LoadLane) error
+	// compileV128Store adds instructions which are equivalent to wasm.OpcodeVecV128StoreName.
 	compileV128Store(o *wazeroir.OperationV128Store) error
+	// compileV128StoreLane adds instructions which are equivalent to wasm.OpcodeVecV128StoreXXLane instructions.
+	// See wasm.OpcodeVecV128Load8LaneName wasm.OpcodeVecV128Load16LaneName wasm.OpcodeVecV128Load32LaneName wasm.OpcodeVecV128Load64LaneName.
 	compileV128StoreLane(o *wazeroir.OperationV128StoreLane) error
+	// compileV128ExtractLane adds instructions which are equivalent to wasm.OpcodeVecXXXXExtractLane instructions.
+	// See wasm.OpcodeVecI8x16ExtractLaneSName wasm.OpcodeVecI8x16ExtractLaneUName wasm.OpcodeVecI16x8ExtractLaneSName wasm.OpcodeVecI16x8ExtractLaneUName
+	// wasm.OpcodeVecI32x4ExtractLaneName wasm.OpcodeVecI64x2ExtractLaneName wasm.OpcodeVecF32x4ExtractLaneName wasm.OpcodeVecF64x2ExtractLaneName.
 	compileV128ExtractLane(o *wazeroir.OperationV128ExtractLane) error
+	// compileV128ReplaceLane adds instructions which are equivalent to wasm.OpcodeVecXXXXReplaceLane instructions.
+	// See wasm.OpcodeVecI8x16ReplaceLaneName wasm.OpcodeVecI16x8ReplaceLaneName wasm.OpcodeVecI32x4ReplaceLaneName wasm.OpcodeVecI64x2ReplaceLaneName
+	// wasm.OpcodeVecF32x4ReplaceLaneName wasm.OpcodeVecF64x2ReplaceLaneName.
 	compileV128ReplaceLane(o *wazeroir.OperationV128ReplaceLane) error
+	// compileV128Splat adds instructions which are equivalent to wasm.OpcodeVecXXXSplat instructions.
+	// See wasm.OpcodeVecI8x16SplatName wasm.OpcodeVecI16x8SplatName wasm.OpcodeVecI32x4SplatName wasm.OpcodeVecI64x2SplatName
+	// wasm.OpcodeVecF32x4SplatName wasm.OpcodeVecF64x2SplatName.
 	compileV128Splat(o *wazeroir.OperationV128Splat) error
+	// compileV128Shuffle adds instructions which are equivalent to wasm.OpcodeVecV128i8x16ShuffleName instruction.
 	compileV128Shuffle(o *wazeroir.OperationV128Shuffle) error
+	// compileV128Swizzle adds instructions which are equivalent to wasm.OpcodeVecI8x16SwizzleName instruction.
 	compileV128Swizzle(o *wazeroir.OperationV128Swizzle) error
+	// compileV128Swizzle adds instructions which are equivalent to wasm.OpcodeVecV128AnyTrueName instruction.
 	compileV128AnyTrue(o *wazeroir.OperationV128AnyTrue) error
+	// compileV128AllTrue adds instructions which are equivalent to wasm.OpcodeVecXXXAllTrue instructions.
+	// See wasm.OpcodeVecI8x16AllTrueName wasm.OpcodeVecI16x8AllTrueName wasm.OpcodeVecI32x4AllTrueName wasm.OpcodeVecI64x2AllTrueName.
 	compileV128AllTrue(o *wazeroir.OperationV128AllTrue) error
 }