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Signed-off-by: Takeshi Yoneda <[email protected]>
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@mathetake
mathetake committed May 27, 2022
1 parent d5e87e7 commit 70fdb0d
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Showing 8 changed files with 67 additions and 57 deletions.
2 changes: 1 addition & 1 deletion internal/asm/arm64/impl.go
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Original file line number Diff line number Diff line change
Expand Up @@ -2599,7 +2599,7 @@ func (a *AssemblerImpl) EncodeMemoryToVectorRegister(n *NodeImpl) (err error) {
}
const v = 1 // v as in https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Loads-and-Stores?lang=en#ldst_pos
err = a.encodeLoadOrStoreWithConstOffset(srcBaseRegBits, dstVectorRegBits,
n.DstConst, opcode, size, v, dataSize, dataSizeLog2)
n.SrcConst, opcode, size, v, dataSize, dataSizeLog2)
default:
return errorEncodingUnsupported(n)
}
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69 changes: 36 additions & 33 deletions internal/asm/arm64/impl_test.go
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Original file line number Diff line number Diff line change
Expand Up @@ -387,11 +387,11 @@ func Test_CompileConditionalRegisterSet(t *testing.T) {

func Test_CompileMemoryToVectorRegister(t *testing.T) {
a := NewAssemblerImpl(RegR10)
a.CompileMemoryToVectorRegister(VMOV, RegR10, RegR11, RegV3, VectorArrangement1D)
a.CompileMemoryToVectorRegister(VMOV, RegR10, 10, RegV3, VectorArrangement1D)
actualNode := a.Current
require.Equal(t, VMOV, actualNode.Instruction)
require.Equal(t, RegR10, actualNode.SrcReg)
require.Equal(t, RegR11, actualNode.SrcReg2)
require.Equal(t, int64(10), actualNode.SrcConst)
require.Equal(t, RegV3, actualNode.DstReg)
require.Equal(t, OperandTypeMemory, actualNode.Types.src)
require.Equal(t, OperandTypeVectorRegister, actualNode.Types.dst)
Expand All @@ -400,12 +400,12 @@ func Test_CompileMemoryToVectorRegister(t *testing.T) {

func Test_CompileVectorRegisterToMemory(t *testing.T) {
a := NewAssemblerImpl(RegR10)
a.CompileVectorRegisterToMemory(VMOV, RegV3, RegR10, RegR30, VectorArrangement1D)
a.CompileVectorRegisterToMemory(VMOV, RegV3, RegR10, 12, VectorArrangement1D)
actualNode := a.Current
require.Equal(t, VMOV, actualNode.Instruction)
require.Equal(t, RegV3, actualNode.SrcReg)
require.Equal(t, RegR10, actualNode.DstReg)
require.Equal(t, RegR30, actualNode.DstReg2)
require.Equal(t, int64(12), actualNode.DstConst)
require.Equal(t, OperandTypeVectorRegister, actualNode.Types.src)
require.Equal(t, OperandTypeMemory, actualNode.Types.dst)
require.Equal(t, VectorArrangement1D, actualNode.VectorArrangement)
Expand Down Expand Up @@ -503,59 +503,59 @@ func TestAssemblerImpl_EncodeVectorRegisterToMemory(t *testing.T) {
exp []byte
}{
{
name: "str b11, [x12, w30, uxtw]",
name: "str b11, [x12, #0x7b]",
n: &NodeImpl{
Instruction: VMOV,
SrcReg: RegV11,
DstReg: RegR12,
DstReg2: RegR30,
DstConst: 0x7b,
VectorArrangement: VectorArrangementB,
},
exp: []byte{0x8b, 0x49, 0x3e, 0x3c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
exp: []byte{0x8b, 0xed, 0x1, 0x3d, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
},
{
name: "str h11, [x12, w30, uxtw]",
name: "ldr w10, #0xc ; str h11, [x12, x10]",
n: &NodeImpl{
Instruction: VMOV,
SrcReg: RegV11,
DstReg: RegR12,
DstReg2: RegR30,
DstConst: 1 << 30,
VectorArrangement: VectorArrangementH,
},
exp: []byte{0x8b, 0x49, 0x3e, 0x7c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
exp: []byte{0x6a, 0x0, 0x0, 0x18, 0x8b, 0x69, 0x2a, 0x7c, 0x0, 0x0, 0x0, 0x14, 0x0, 0x0, 0x0, 0x40},
},
{
name: "str s11, [x12, w30, uxtw]",
name: "ldr w10, #0xc ; str s11, [x12, x10]",
n: &NodeImpl{
Instruction: VMOV,
SrcReg: RegV11,
DstReg: RegR12,
DstReg2: RegR30,
DstConst: (1 << 28) + 4,
VectorArrangement: VectorArrangementS,
},
exp: []byte{0x8b, 0x49, 0x3e, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
exp: []byte{0x6a, 0x0, 0x0, 0x18, 0x8b, 0x69, 0x2a, 0xbc, 0x0, 0x0, 0x0, 0x14, 0x4, 0x0, 0x0, 0x10},
},
{
name: "str d11, [x12, w30, uxtw]",
name: "str d11, [x12, #0x3d8]",
n: &NodeImpl{
Instruction: VMOV,
SrcReg: RegV11,
DstReg: RegR12,
DstReg2: RegR30,
DstConst: 0x3d8,
VectorArrangement: VectorArrangementD,
},
exp: []byte{0x8b, 0x49, 0x3e, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
exp: []byte{0x8b, 0xed, 0x1, 0xfd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
},
{
name: "str q1, [x30, wzr, uxtw]",
name: "str q1, [x30]",
n: &NodeImpl{
Instruction: VMOV,
SrcReg: RegV1,
DstReg: RegR30,
DstReg2: RegRZR,
DstConst: 0,
VectorArrangement: VectorArrangementQ,
},
exp: []byte{0xc1, 0x4b, 0xbf, 0x3c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
exp: []byte{0xc1, 0x3, 0x80, 0x3d, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
},
}

Expand All @@ -566,6 +566,8 @@ func TestAssemblerImpl_EncodeVectorRegisterToMemory(t *testing.T) {
err := a.EncodeVectorRegisterToMemory(tc.n)
require.NoError(t, err)

a.maybeFlushConstPool(true)

actual, err := a.Assemble()
require.NoError(t, err)
require.Equal(t, tc.exp, actual, hex.EncodeToString(actual))
Expand All @@ -581,59 +583,58 @@ func TestAssemblerImpl_EncodeMemoryToVectorRegister(t *testing.T) {
exp []byte
}{
{
name: "ldr b11, [x12, w30, uxtw]",
name: "ldr b11, [x12, #0x7b]",
n: &NodeImpl{
Instruction: VMOV,
SrcReg: RegR12,
SrcReg2: RegR30,
SrcConst: 0x7b,
DstReg: RegV11,
VectorArrangement: VectorArrangementB,
},
exp: []byte{0x8b, 0x49, 0x7e, 0x3c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
exp: []byte{0x8b, 0xed, 0x41, 0x3d, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
},
{
name: "str h11, [x12, w30, uxtw]",
n: &NodeImpl{
Instruction: VMOV,
DstReg: RegV11,
SrcReg: RegR12,
SrcReg2: RegR30,
VectorArrangement: VectorArrangementH,
},
exp: []byte{0x8b, 0x49, 0x7e, 0x7c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
exp: []byte{0x8b, 0x1, 0x40, 0x7d, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
},
{
name: "ldr s11, [x12, w30, uxtw]",
name: "ldr w10, #0xc ; ldr s11, [x12, x10]",
n: &NodeImpl{
Instruction: VMOV,
DstReg: RegV11,
SrcReg: RegR12,
SrcReg2: RegR30,
SrcConst: 1 << 28,
VectorArrangement: VectorArrangementS,
},
exp: []byte{0x8b, 0x49, 0x7e, 0xbc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
exp: []byte{0x6a, 0x0, 0x0, 0x18, 0x8b, 0x69, 0x6a, 0xbc, 0x0, 0x0, 0x0, 0x14, 0x0, 0x0, 0x0, 0x10},
},
{
name: "ldr d11, [x12, w30, uxtw]",
name: "ldr w10, #0xc ; ldr d11, [x12, x10]",
n: &NodeImpl{
Instruction: VMOV,
DstReg: RegV11,
SrcReg: RegR12,
SrcReg2: RegR30,
SrcConst: 1<<29 + 4,
VectorArrangement: VectorArrangementD,
},
exp: []byte{0x8b, 0x49, 0x7e, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
exp: []byte{0x6a, 0x0, 0x0, 0x18, 0x8b, 0x69, 0x6a, 0xfc, 0x0, 0x0, 0x0, 0x14, 0x4, 0x0, 0x0, 0x20},
},
{
name: "ldr q1, [x30, wzr, uxtw]",
name: "ldr w10, #0xc ; ldr q1, [x30, x10]",
n: &NodeImpl{
Instruction: VMOV,
DstReg: RegV1,
SrcReg: RegR30,
SrcReg2: RegRZR,
SrcConst: 1<<17 + 4,
VectorArrangement: VectorArrangementQ,
},
exp: []byte{0xc1, 0x4b, 0xff, 0x3c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
exp: []byte{0x6a, 0x0, 0x0, 0x18, 0xc1, 0x6b, 0xea, 0x3c, 0x0, 0x0, 0x0, 0x14, 0x4, 0x0, 0x2, 0x0},
},
}

Expand All @@ -644,6 +645,8 @@ func TestAssemblerImpl_EncodeMemoryToVectorRegister(t *testing.T) {
err := a.EncodeMemoryToVectorRegister(tc.n)
require.NoError(t, err)

a.maybeFlushConstPool(true)

actual, err := a.Assemble()
require.NoError(t, err)
require.Equal(t, tc.exp, actual, hex.EncodeToString(actual))
Expand Down
2 changes: 2 additions & 0 deletions internal/engine/compiler/compiler_stack_test.go
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Original file line number Diff line number Diff line change
Expand Up @@ -620,6 +620,8 @@ func TestCompiler_compileSwap_v128(t *testing.T) {
if tc.x1OnRegister {
err = compiler.compileV128Const(&wazeroir.OperationV128Const{Lo: x1Lo, Hi: x1Hi})
require.NoError(t, err)
env.stack()[0] = 0xff
env.stack()[1] = 0xff
} else {
lo := compiler.runtimeValueLocationStack().pushRuntimeValueLocationOnStack() // lo
lo.valueType = runtimeValueTypeV128Lo
Expand Down
1 change: 1 addition & 0 deletions internal/engine/compiler/impl_arm64.go
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Original file line number Diff line number Diff line change
Expand Up @@ -484,6 +484,7 @@ func (c *arm64Compiler) compileSwap(o *wazeroir.OperationSwap) error {
if err := c.compileEnsureOnGeneralPurposeRegister(x); err != nil {
return err
}

if err := c.compileEnsureOnGeneralPurposeRegister(y); err != nil {
return err
}
Expand Down
12 changes: 7 additions & 5 deletions internal/integration_test/asm/arm64_debug/debug_assembler.go
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Original file line number Diff line number Diff line change
Expand Up @@ -255,16 +255,18 @@ func (ta *testAssembler) CompileConditionalRegisterSet(cond asm.ConditionalRegis
ta.a.CompileConditionalRegisterSet(cond, dstReg)
}

func (ta *testAssembler) CompileMemoryToVectorRegister(instruction asm.Instruction, srcOffsetReg, dstReg asm.Register,
func (ta *testAssembler) CompileMemoryToVectorRegister(instruction asm.Instruction, srcOffsetReg asm.Register,
c asm.ConstantValue, dstReg asm.Register,
arrangement arm64.VectorArrangement) {
ta.goasm.CompileMemoryToVectorRegister(instruction, srcOffsetReg, dstReg, arrangement)
ta.a.CompileMemoryToVectorRegister(instruction, srcOffsetReg, dstReg, arrangement)
ta.goasm.CompileMemoryToVectorRegister(instruction, srcOffsetReg, c, dstReg, arrangement)
ta.a.CompileMemoryToVectorRegister(instruction, srcOffsetReg, c, dstReg, arrangement)
}

func (ta *testAssembler) CompileVectorRegisterToMemory(instruction asm.Instruction, srcReg, dstOffsetReg asm.Register,
c asm.ConstantValue,
arrangement arm64.VectorArrangement) {
ta.goasm.CompileVectorRegisterToMemory(instruction, srcReg, dstOffsetReg, arrangement)
ta.a.CompileVectorRegisterToMemory(instruction, srcReg, dstOffsetReg, arrangement)
ta.goasm.CompileVectorRegisterToMemory(instruction, srcReg, dstOffsetReg, c, arrangement)
ta.a.CompileVectorRegisterToMemory(instruction, srcReg, dstOffsetReg, c, arrangement)
}

func (ta *testAssembler) CompileRegisterToVectorRegister(instruction asm.Instruction, srcReg, dstReg asm.Register,
Expand Down
4 changes: 2 additions & 2 deletions internal/integration_test/asm/arm64_debug/golang_asm.go
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Original file line number Diff line number Diff line change
Expand Up @@ -333,12 +333,12 @@ func (a *assemblerGoAsmImpl) CompileSIMDByteToRegister(instruction asm.Instructi
}

func (a *assemblerGoAsmImpl) CompileMemoryToVectorRegister(
_ asm.Instruction, _, _, _ asm.Register, _ asm_arm64.VectorArrangement,
_ asm.Instruction, _ asm.Register, _ asm.ConstantValue, _ asm.Register, _ asm_arm64.VectorArrangement,
) {
panic("CompileMemoryToVectorRegister is unsupported with golang-asm")
}

func (a *assemblerGoAsmImpl) CompileVectorRegisterToMemory(_ asm.Instruction, _, _, _ asm.Register,
func (a *assemblerGoAsmImpl) CompileVectorRegisterToMemory(_ asm.Instruction, _, _ asm.Register, _ asm.ConstantValue,
_ asm_arm64.VectorArrangement) {
panic("CompileVectorRegisterToMemory is unsupported with golang-asm")
}
Expand Down
2 changes: 2 additions & 0 deletions internal/integration_test/asm/arm64_debug/impl_test.go
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Original file line number Diff line number Diff line change
Expand Up @@ -880,6 +880,7 @@ func TestAssemblerImpl_EncodeRegisterToMemory(t *testing.T) {
-1, 0, 1, 2, -2, 4, -4, 0xf, -0xf, 1 << 4, 1<<4 - 1, 1<<4 + 1, -128, -256, 8 * 10, -128,
255, 4096, 4096 << 1, 32760, 32760 * 2, 32760*2 - 8,
32760*2 - 16, 1 << 27, 1 << 30, 1<<30 + 8, 1<<30 - 8, 1<<30 + 16, 1<<30 - 16, 1<<31 - 8,
(1 << 28) + 4,
}
intRegs := []asm.Register{
arm64.RegR0, arm64.RegR16,
Expand Down Expand Up @@ -978,6 +979,7 @@ func TestAssemblerImpl_EncodeMemoryToRegister(t *testing.T) {
-1, 0, 1, 2, -2, 0xf, -0xf, 1 << 4, 1<<4 - 1, 1<<4 + 1, -128, -256, 8 * 10, -128,
255, 4096, 4096 << 1, 32760, 32760 * 2, 32760*2 - 8,
32760*2 - 16, 1 << 27, 1 << 30, 1<<30 + 8, 1<<30 - 8, 1<<30 + 16, 1<<30 - 16, 1<<31 - 8,
(1 << 28) + 4,
1<<12<<8 + 8,
1<<12<<8 - 8,
}
Expand Down
32 changes: 16 additions & 16 deletions internal/integration_test/spectest/v2/spec_test.go
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Original file line number Diff line number Diff line change
Expand Up @@ -28,28 +28,28 @@ func TestCompiler(t *testing.T) {
// TODO: remove after SIMD proposal
if strings.Contains(jsonname, "simd") {
switch path.Base(jsonname) {
//case "simd_address.json":
case "simd_address.json":
case "simd_const.json":
//case "simd_align.json":
//case "simd_load16_lane.json":
//case "simd_load32_lane.json":
//case "simd_load64_lane.json":
//case "simd_load8_lane.json":
//case "simd_lane.json":
//case "simd_load_extend.json":
//case "simd_load_splat.json":
//case "simd_load_zero.json":
//case "simd_store.json":
//case "simd_store16_lane.json":
//case "simd_store32_lane.json":
//case "simd_store64_lane.json":
//case "simd_store8_lane.json":
case "simd_align.json":
case "simd_load16_lane.json":
case "simd_load32_lane.json":
case "simd_load64_lane.json":
case "simd_load8_lane.json":
case "simd_lane.json":
case "simd_load_extend.json":
case "simd_load_splat.json":
case "simd_load_zero.json":
case "simd_store.json":
case "simd_store16_lane.json":
case "simd_store32_lane.json":
case "simd_store64_lane.json":
case "simd_store8_lane.json":
default:
return false
}
return true
}
return false
return true
})
}

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