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[type] Fix arm64 flush to zero #2148

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merged 4 commits into from
Jan 10, 2021
Merged

[type] Fix arm64 flush to zero #2148

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a1becf1
[type] Fix arm64 flush to zero
yuanming-hu Jan 10, 2021
ac0ff89
[skip ci] enforce code format
taichi-gardener Jan 10, 2021
6ac7522
fix
yuanming-hu Jan 10, 2021
4234f05
Merge branch 'quant5' into arm64-ftz
yuanming-hu Jan 10, 2021
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2 changes: 1 addition & 1 deletion python/taichi/lang/snode.py
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ def bitmasked(self, indices, dimensions):
dimensions = [dimensions] * len(indices)
return SNode(self.ptr.bitmasked(indices, dimensions))

@deprecated('_bit_array', 'bit_array')
@deprecated('_bit_struct', 'bit_struct')
def _bit_struct(self, num_bits):
return self.bit_struct(num_bits)

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16 changes: 16 additions & 0 deletions taichi/program/program.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,10 @@
#include "taichi/backends/cc/codegen_cc.h"
#endif

#if defined(TI_ARCH_x64)
// For _MM_SET_FLUSH_ZERO_MODE
#include <xmmintrin.h>
#endif

TI_NAMESPACE_BEGIN

Expand Down Expand Up @@ -68,7 +71,20 @@ Program::Program(Arch desired_arch) {
// For performance considerations and correctness of CustomFloatType
// operations, we force floating-point operations to flush to zero on all
// backends (including CPUs).
#if defined(TI_ARCH_x64)
_MM_SET_FLUSH_ZERO_MODE(_MM_FLUSH_ZERO_ON);
#else
// Enforce flush to zero on arm64 CPUs
// https://developer.arm.com/documentation/100403/0201/register-descriptions/advanced-simd-and-floating-point-registers/aarch64-register-descriptions/fpcr--floating-point-control-register?lang=en
std::uint64_t fpcr;
__asm__ __volatile__("");
__asm__ __volatile__("MRS %0, FPCR" : "=r"(fpcr));
__asm__ __volatile__("");
__asm__ __volatile__("MSR FPCR, %0"
:
: "ri"(fpcr | (1 << 24))); // Bit 24 is FZ
__asm__ __volatile__("");
#endif

auto arch = desired_arch;
if (arch == Arch::cuda) {
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