GitHub - suti333/PipelinedProcessor: Simulation of a 5-stage Pipelined Processor with static branch prediction in SystemVerilog, based on a custom MIPS instruction set and benchmarked the processor for a given set of tasks.

suti333 / PipelinedProcessor Public

Notifications You must be signed in to change notification settings
Fork 1
Star 0

Simulation of a 5-stage Pipelined Processor with static branch prediction in SystemVerilog, based on a custom MIPS instruction set and benchmarked the processor for a given set of tasks.

0 stars 1 fork Branches Tags Activity

Star

Notifications

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ALU		ALU
ALUControl		ALUControl
ControlUnit		ControlUnit
DataMem		DataMem
EXMEMReg		EXMEMReg
FlushUnit		FlushUnit
IDEXReg		IDEXReg
IFIDReg		IFIDReg
InstrMem		InstrMem
MEMWBReg		MEMWBReg
MUX32		MUX32
MUX5		MUX5
PCReg		PCReg
PipelinedProcessor		PipelinedProcessor
RegFile		RegFile
SignExtention		SignExtention
StallControlUnit1		StallControlUnit1
StallControlUnit2		StallControlUnit2
PARSED_assembly_code.txt		PARSED_assembly_code.txt
assemble_1.cpp		assemble_1.cpp
assemble_1.exe		assemble_1.exe
assembly_code.txt		assembly_code.txt
assembly_code1.txt		assembly_code1.txt
assembly_code2.txt		assembly_code2.txt

About

Simulation of a 5-stage Pipelined Processor with static branch prediction in SystemVerilog, based on a custom MIPS instruction set and benchmarked the processor for a given set of tasks.

Activity

0 stars

1 watching

1 fork

Report repository