⚠️ rework ONEWIRE and GPTMR interrupts #859
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keep interrupt pending until explicitly cleared by writing zero to interrupt trigger state bit(s)
interrupt will stay active as long as the module is in idle state
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The interrupt of the ONEWIRE module will now become set whenever the module is in idle state (e.g. after completing an operation).
The GPTMR timer interrupt will now remain pending until explicitly cleared by writing zero to the module's
GPTMR_CTRL_TRIGMand/orGPTMR_CTRL_TRIGCcontrol register bits (depneing on the interrupt trigger configuration).Note
This PR is part of a series that aims to unify (and simplify) the entire interrupt system of the processor.