Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

🐛 Fix write access to mip.firq CSR bits #821

Merged
merged 3 commits into from
Feb 21, 2024
Merged

Conversation

stnolting
Copy link
Owner

@stnolting stnolting commented Feb 20, 2024

Fixing #818

Write accesses to the mip FIRQ CSR bits always impacted all FIRQ bits (making clearing/acknowledging a single FIRQ impossible). As a side-effect of this fix the mip.firq bits are now read-write. Hence, software can trigger FIRQ manually by writing 1 to the according FIRQ bits.

@stnolting stnolting added bug Something isn't working as expected HW Hardware-related labels Feb 20, 2024
@stnolting stnolting self-assigned this Feb 20, 2024
@stnolting stnolting linked an issue Feb 20, 2024 that may be closed by this pull request
@stnolting stnolting marked this pull request as ready for review February 20, 2024 22:50
@stnolting stnolting merged commit d0c3cfa into main Feb 21, 2024
8 checks passed
@stnolting stnolting deleted the fix_mip_firq_access branch February 21, 2024 16:15
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
bug Something isn't working as expected HW Hardware-related
Projects
None yet
Development

Successfully merging this pull request may close these issues.

Possible issue with FIRQ pending interrupt clearing
1 participant