Minor rtl optimizations and cleanups

CHANGELOG.md

@@ -32,6 +32,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 29.09.2023 | 1.8.9.5 | minor CPU optimizations and code clean-ups; [#694](https://github.com/stnolting/neorv32/pull/694) |
 | 23.09.2023 | 1.8.9.4 | :sparkles: added vectored trap handling mode of `mtvec` for reduced latency from IRQ to ISR; [#691](https://github.com/stnolting/neorv32/pull/691)
 | 22.09.2023 | 1.8.9.3 | :lock: **watchdog**: add reset password and optional "strict" mode for increased safety; [#692](https://github.com/stnolting/neorv32/pull/692) |
 | 15.09.2023 | 1.8.9.2 | :warning: rework CFU CSRs; minor rtl edits; [#690](https://github.com/stnolting/neorv32/pull/690) |

docs/datasheet/cpu.adoc

@@ -462,7 +462,7 @@ The `I` ISA extensions is the base RISC-V integer ISA that is always enabled.
 | Jump/call     | `jal[r]`                                                                  | 6
 | Load/store    | `lb` `lh` `lw` `lbu` `lhu` `sb` `sh` `sw`                                 | 5
 | System        | `ecall` `ebreak`                                                          | 3
-| Data fence    | `fence`                                                                   | 5
+| Data fence    | `fence`                                                                   | 3
 | System        | `wfi`                                                                     | 3
 | System        | `mret`                                                                    | 5
 | Illegal inst. | -                                                                         | 3

rtl/core/neorv32_cpu.vhd

@@ -122,7 +122,7 @@ architecture neorv32_cpu_rtl of neorv32_cpu is
   signal alu_cmp     : std_ulogic_vector(1 downto 0); -- comparator result
   signal mem_rdata   : std_ulogic_vector(XLEN-1 downto 0); -- memory read data
   signal cp_done     : std_ulogic; -- ALU co-processor operation done
-  signal bus_d_wait  : std_ulogic; -- wait for current data bus access
+  signal lsu_wait    : std_ulogic; -- wait for current data bus access
   signal csr_rdata   : std_ulogic_vector(XLEN-1 downto 0); -- csr read data
   signal mar         : std_ulogic_vector(XLEN-1 downto 0); -- memory address register
   signal ma_load     : std_ulogic; -- misaligned load data address
@@ -218,47 +218,45 @@ begin
   )
   port map (
     -- global control --
-    clk_i         => clk_i,           -- global clock, rising edge
-    rstn_i        => rstn_i,          -- global reset, low-active, async
-    ctrl_o        => ctrl,            -- main control bus
+    clk_i         => clk_i,          -- global clock, rising edge
+    rstn_i        => rstn_i,         -- global reset, low-active, async
+    ctrl_o        => ctrl,           -- main control bus
     -- instruction fetch interface --
-    i_bus_addr_o  => fetch_pc,        -- bus access address
-    i_bus_rdata_i => ibus_rsp_i.data, -- bus read data
-    i_bus_re_o    => ibus_req_o.re,   -- read enable
-    i_bus_ack_i   => ibus_rsp_i.ack,  -- bus transfer acknowledge
-    i_bus_err_i   => ibus_rsp_i.err,  -- bus transfer error
-    i_pmp_fault_i => pmp_i_fault,     -- instruction fetch pmp fault
+    bus_req_o     => ibus_req_o,     -- request
+    bus_rsp_i     => ibus_rsp_i,     -- response
     -- status input --
-    alu_cp_done_i => cp_done,         -- ALU iterative operation done
-    bus_d_wait_i  => bus_d_wait,      -- wait for bus
+    i_pmp_fault_i => pmp_i_fault,    -- instruction fetch pmp fault
+    alu_cp_done_i => cp_done,        -- ALU iterative operation done
+    lsu_wait_i    => lsu_wait,       -- wait for data bus
+    cmp_i         => alu_cmp,        -- comparator status
     -- data input --
-    cmp_i         => alu_cmp,         -- comparator status
-    alu_add_i     => alu_add,         -- ALU address result
-    rs1_i         => rs1,             -- rf source 1
+    alu_add_i     => alu_add,        -- ALU address result
+    rs1_i         => rs1,            -- rf source 1
     -- data output --
-    imm_o         => imm,             -- immediate
-    curr_pc_o     => curr_pc,         -- current PC (corresponding to current instruction)
-    next_pc_o     => next_pc,         -- next PC (corresponding to next instruction)
-    csr_rdata_o   => csr_rdata,       -- CSR read data
+    imm_o         => imm,            -- immediate
+    fetch_pc_o    => fetch_pc,       -- instruction fetch address
+    curr_pc_o     => curr_pc,        -- current PC (corresponding to current instruction)
+    next_pc_o     => next_pc,        -- next PC (corresponding to next instruction)
+    csr_rdata_o   => csr_rdata,      -- CSR read data
     -- external CSR interface --
-    xcsr_we_o     => xcsr_we,         -- global write enable
-    xcsr_addr_o   => xcsr_addr,       -- address
-    xcsr_wdata_o  => xcsr_wdata,      -- write data
-    xcsr_rdata_i  => xcsr_rdata_res,  -- read data
+    xcsr_we_o     => xcsr_we,        -- global write enable
+    xcsr_addr_o   => xcsr_addr,      -- address
+    xcsr_wdata_o  => xcsr_wdata,     -- write data
+    xcsr_rdata_i  => xcsr_rdata_res, -- read data
     -- debug mode (halt) request --
     db_halt_req_i => dbi_i,
     -- interrupts (risc-v compliant) --
-    msi_i         => msi_i,           -- machine software interrupt
-    mei_i         => mei_i,           -- machine external interrupt
-    mti_i         => mti_i,           -- machine timer interrupt
+    msi_i         => msi_i,          -- machine software interrupt
+    mei_i         => mei_i,          -- machine external interrupt
+    mti_i         => mti_i,          -- machine timer interrupt
     -- fast interrupts (custom) --
-    firq_i        => firq_i,          -- fast interrupt trigger
+    firq_i        => firq_i,         -- fast interrupt trigger
     -- bus access exceptions --
-    mar_i         => mar,             -- memory address register
-    ma_load_i     => ma_load,         -- misaligned load data address
-    ma_store_i    => ma_store,        -- misaligned store data address
-    be_load_i     => be_load,         -- bus error on load data access
-    be_store_i    => be_store         -- bus error on store data access
+    mar_i         => mar,            -- memory address register
+    ma_load_i     => ma_load,        -- misaligned load data address
+    ma_store_i    => ma_store,       -- misaligned store data address
+    be_load_i     => be_load,        -- bus error on load data access
+    be_store_i    => be_store        -- bus error on store data access
   );
 
   -- external CSR read-back --
@@ -272,15 +270,6 @@ begin
   ifence_o <= ctrl.lsu_fencei;
   dfence_o <= ctrl.lsu_fence;
 
-  -- instruction fetch interface --
-  ibus_req_o.addr <= fetch_pc;
-  ibus_req_o.priv <= ctrl.cpu_priv;
-  ibus_req_o.data <= (others => '0'); -- read-only
-  ibus_req_o.ben  <= (others => '0'); -- read-only
-  ibus_req_o.we   <= '0'; -- read-only
-  ibus_req_o.src  <= '1'; -- source = instruction fetch
-  ibus_req_o.rvso <= '0'; -- cannot be a reservation set operation
-
 
   -- Register File --------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
@@ -355,37 +344,26 @@ begin
   )
   port map (
     -- global control --
-    clk_i         => clk_i,           -- global clock, rising edge
-    rstn_i        => rstn_i,          -- global reset, low-active, async
-    ctrl_i        => ctrl,            -- main control bus
+    clk_i         => clk_i,       -- global clock, rising edge
+    rstn_i        => rstn_i,      -- global reset, low-active, async
+    ctrl_i        => ctrl,        -- main control bus
     -- cpu data access interface --
-    addr_i        => alu_add,         -- access address
-    wdata_i       => rs2,             -- write data
-    rdata_o       => mem_rdata,       -- read data
-    mar_o         => mar,             -- memory address register
-    d_wait_o      => bus_d_wait,      -- wait for access to complete
-    ma_load_o     => ma_load,         -- misaligned load data address
-    ma_store_o    => ma_store,        -- misaligned store data address
-    be_load_o     => be_load,         -- bus error on load data access
-    be_store_o    => be_store,        -- bus error on store data access
-    pmp_r_fault_i => pmp_r_fault,     -- PMP read fault
-    pmp_w_fault_i => pmp_w_fault,     -- PMP write fault
+    addr_i        => alu_add,     -- access address
+    wdata_i       => rs2,         -- write data
+    rdata_o       => mem_rdata,   -- read data
+    mar_o         => mar,         -- memory address register
+    wait_o        => lsu_wait,    -- wait for access to complete
+    ma_load_o     => ma_load,     -- misaligned load data address
+    ma_store_o    => ma_store,    -- misaligned store data address
+    be_load_o     => be_load,     -- bus error on load data access
+    be_store_o    => be_store,    -- bus error on store data access
+    pmp_r_fault_i => pmp_r_fault, -- PMP read fault
+    pmp_w_fault_i => pmp_w_fault, -- PMP write fault
     -- data bus --
-    d_bus_addr_o  => dbus_req_o.addr, -- bus access address
-    d_bus_rdata_i => dbus_rsp_i.data, -- bus read data
-    d_bus_wdata_o => dbus_req_o.data, -- bus write data
-    d_bus_ben_o   => dbus_req_o.ben,  -- byte enable
-    d_bus_we_o    => dbus_req_o.we,   -- write enable
-    d_bus_re_o    => dbus_req_o.re,   -- read enable
-    d_bus_ack_i   => dbus_rsp_i.ack,  -- bus transfer acknowledge
-    d_bus_err_i   => dbus_rsp_i.err   -- bus transfer error
+    bus_req_o     => dbus_req_o,  -- request
+    bus_rsp_i     => dbus_rsp_i   -- response
   );
 
-  -- data access interface --
-  dbus_req_o.priv <= ctrl.lsu_priv;
-  dbus_req_o.src  <= '0'; -- source = data access
-  dbus_req_o.rvso <= ctrl.lsu_rvso when (CPU_EXTENSION_RISCV_A = true) else '0'; -- is LR/SC reservation set operation
-
 
   -- Physical Memory Protection -------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------

rtl/core/neorv32_cpu_alu.vhd

@@ -140,7 +140,8 @@ begin
       when alu_op_add_c  => res_o <= addsub_res(XLEN-1 downto 0);
       when alu_op_sub_c  => res_o <= addsub_res(XLEN-1 downto 0);
       when alu_op_cp_c   => res_o <= cp_res;
-      when alu_op_slt_c  => res_o <= (others => '0'); res_o(0) <= addsub_res(addsub_res'left); -- carry/borrow
+      when alu_op_slt_c  => res_o(XLEN-1 downto 1) <= (others => '0');
+                            res_o(0) <= addsub_res(addsub_res'left); -- carry/borrow
       when alu_op_movb_c => res_o <= opb;
       when alu_op_xor_c  => res_o <= rs1_i xor opb; -- only rs1 is required for logic ops (opa would also contain pc)
       when alu_op_or_c   => res_o <= rs1_i or  opb;