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Add Smcntrpmf ISA extension #676

Merged
merged 8 commits into from
Aug 24, 2023
Merged

Add Smcntrpmf ISA extension #676

merged 8 commits into from
Aug 24, 2023

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stnolting
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@stnolting stnolting commented Aug 23, 2023

  • ✨ add support for the Smcntrpmf ISA extension ("counter privilege mode filtering")
    • add four new CSRs: mcyclecfg[h] and minstretcfg[h]
    • allows to halt the CYCLE and INSTRET counter when the CPU is in a specific privilege mode
    • 🧪 extension is frozen but not yet ratified
    • this extension is always enabled when the U ISA extension is enabled
  • remove menvcfg[h] CSRs - these were unused and hardwired to all-zero anyway
  • mcounteren CSR is only available when U ISA extension is enabled (required by RISC-V priv. spec.)

@stnolting stnolting added enhancement New feature or request risc-v compliance Modification to comply with official RISC-V specs. HW Hardware-related labels Aug 23, 2023
@stnolting stnolting self-assigned this Aug 23, 2023
@stnolting stnolting marked this pull request as ready for review August 23, 2023 20:33
@stnolting stnolting merged commit aeaf116 into main Aug 24, 2023
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@stnolting stnolting deleted the smcntrpmf branch August 24, 2023 16:24
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enhancement New feature or request HW Hardware-related risc-v compliance Modification to comply with official RISC-V specs.
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