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This PR adds an automatic transfer trigger to the processor's DMA controller.
Instead of starting a transfer by writing to a specific DMA register, the DMA can be configured to start a previously programmed transfer when a specific processor-internal module issues an interrupt request.
Exemplary Use Case
The TRNG (true-random number generator) is configured with a FIFO depth of 64 entries using the according generic. The application code configures the TRNG interrupt to fire if the FIFO is completely full - indicating that 64 bytes of entropy have been sampled.
A DMA transfer is programmed to read bytes (constant address) from TRNG (= the entropy data) and to store it to a 64-bytes array in memory (incrementing address). The automatic trigger mode is used to start the transfer when the TRNG sends the "FIFO full" interrupt.
Enabling just the DMA interrupt in the CPU's
mie
CSR will trigger an interrupt when the DMA transfer is complete (but not when the TRNG issues its FIFO full interrupt).