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⚠️ Rework CPU counters #477
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stnolting
added
risc-v compliance
Modification to comply with official RISC-V specs.
HW
Hardware-related
coding-style
Related to the HW/SW coding style
labels
Jan 15, 2023
- remove time[h]CSRs - hardwire mcounteren to all-one - add user-level hpm counter CSRs - rework CSR access check logic
- optimized mcountinhibit CSR logic - clearing mie will no longer also clera mip
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Labels
coding-style
Related to the HW/SW coding style
HW
Hardware-related
optimization
Make things faster, smaller and more efficient
risc-v compliance
Modification to comply with official RISC-V specs.
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mtime_i
andmtime_o
top entity portstime
andtimeh
CSRsmcounteren
CSR to all-one - user-level software is always allowed to access the user-level counter CSRshpmcounter3[h]
tohpmcounter31[h]