Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

🐛 fix SPI & XIP clock phase offset #336

Merged
merged 4 commits into from
Jun 4, 2022
Merged

Conversation

stnolting
Copy link
Owner

@stnolting stnolting commented Jun 3, 2022

This PR fixes the SPI phase offset problem (between SPI clock and SPI data_in/data_out) as described in #335 by @andkae. The XIP module is also affected by this bug and is also fixed by this PR.

ℹ️ This bug is only relevant only when using the SPI/XIP interface at very high clock speeds that are close to the processor's main clock (small clock prescaler or high-speed mode enabled).

@stnolting stnolting added bug Something isn't working as expected HW Hardware-related labels Jun 3, 2022
@stnolting stnolting self-assigned this Jun 3, 2022
@stnolting stnolting linked an issue Jun 3, 2022 that may be closed by this pull request
@stnolting stnolting changed the title 🐛 fix SPI phase offset 🐛 fix SPI & XIP phase offset Jun 3, 2022
@stnolting stnolting changed the title 🐛 fix SPI & XIP phase offset 🐛 fix SPI & XIP clock phase offset Jun 3, 2022
@stnolting stnolting merged commit 6a412d6 into main Jun 4, 2022
@stnolting stnolting deleted the fix_spi_phase_offset branch June 4, 2022 09:06
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
bug Something isn't working as expected HW Hardware-related
Projects
None yet
Development

Successfully merging this pull request may close these issues.

Full SCK cycle shift of MOSI in SPI Mode 0 with activated Highspeed
1 participant