[rtl] optimize CPU barrel shifter timing #301
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move register stage of barrel shifter to improve timing
stnolting
added
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By default, the CPU uses a bit-serial approach for shift instructions (requiring up to 31 additional cycles). If
FAST_SHIFT_ENis true a 2-cycle barrel-shifter is implemented instead. This PR optimizes the timing of the barrel shifter by moving the internal pipeline register.Furthermore, the register balancing of the synthesis tool should now be able to move this pipeline register to further improve timing.