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Move osflow examples #137

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Aug 16, 2021
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4 changes: 2 additions & 2 deletions .github/workflows/Implementation.yml
Original file line number Diff line number Diff line change
Expand Up @@ -48,12 +48,12 @@ jobs:
- name: '🚧 Generate ${{ matrix.board }} ${{ matrix.design }} bitstream'
uses: docker://ghcr.io/stnolting/neorv32/impl
with:
args: make -C setups/examples BOARD=${{ matrix.board }} ${{ matrix.design }}
args: make -C setups/osflow BOARD=${{ matrix.board }} ${{ matrix.design }}

- name: '📤 Upload Artifact: ${{ matrix.board }} ${{ matrix.design }} bitstream and reports'
uses: actions/upload-artifact@v2
with:
name: ${{ matrix.board }}-${{ matrix.design }}
path: |
setups/examples/${{ matrix.bitstream }}
setups/osflow/${{ matrix.bitstream }}
setups/osflow/${{ matrix.board }}/*-report.txt
83 changes: 0 additions & 83 deletions setups/examples/README.md

This file was deleted.

8 changes: 4 additions & 4 deletions setups/examples/Makefile → setups/osflow/Makefile
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
OSFLOW := ../osflow
EXAMPLES := ../examples
OSFLOW := .
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BOARD_TOPS := ./board_tops
TEMPLATES := ../../rtl/templates
MV := mv

Expand All @@ -18,7 +18,7 @@ UPduino_REV ?= v3
run:
$(eval TASK ?= clean $(BITSTREAM))
$(MAKE) -C $(OSFLOW) -f common.mk \
BOARD_SRC=$(EXAMPLES)/neorv32_$(BOARD)_BoardTop_$(DESIGN).vhd \
BOARD_SRC=$(BOARD_TOPS)/neorv32_$(BOARD)_BoardTop_$(DESIGN).vhd \
TOP=neorv32_$(BOARD)_BoardTop_$(DESIGN) \
ID=$(DESIGN) \
$(TASK)
Expand Down Expand Up @@ -81,7 +81,7 @@ MixedLanguage:
$(MAKE) \
DESIGN=$@ \
DESIGN_SRC=$(TEMPLATES)/processor/neorv32_ProcessorTop_Minimal*.vhd \
NEORV32_VERILOG_SRC='devices/ice40/sb_ice40_components.v ../examples/neorv32_Fomu_MixedLanguage_ClkGen.v' \
NEORV32_VERILOG_SRC='devices/ice40/sb_ice40_components.v ../board_tops/neorv32_Fomu_MixedLanguage_ClkGen.v' \
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$(BOARD)

# Help
Expand Down
1 change: 1 addition & 0 deletions setups/osflow/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@ open source toolchains. Synthesis based on [ghdl-yosys](https://github.com/ghdl/
## Folder Structure

* `boards`: board-specific makefiles for generating bitstreams
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* `board_top`: board-specific top entities (board wrappers; may include FPGA-specific modules)
* `constraints`: physical constraints (mainly pin mappings)
* `devices`: FPGA-specific primitives and optimized processor modules (like memories)

Expand Down