[rtl] fix some Verilog [sic] issues #1103
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"config" seems to be a reserved word in Verilog
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Fix some HDL issues that caused problem when converting the code to RTL (https://github.com/stnolting/neorv32-verilog). Identified by @pluseqs in #1100.
configseems to be a reserved word in Verilog