Merge pull request #60 from umarcor/doc/common-include

[docs] add attrs.adoc and attrs.main.adoc
stnolting · Jun 8, 2021 · b5638c8 · b5638c8
2 parents 03b94db + 5b9316f
commit b5638c8
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Showing 6 changed files with 25 additions and 54 deletions.
diff --git a/docs/attrs.adoc b/docs/attrs.adoc
@@ -0,0 +1,12 @@
+:author: Dipl.-Ing. Stephan Nolting
+:email: [email protected]
+:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
+:revnumber: v1.5.6.0
+:doctype: book
+:sectnums:
+:stem:
+:reproducible:
+:listing-caption: Listing
+:toclevels: 4
+:title-logo-image: neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
+:favicon: img/icon.png
diff --git a/docs/attrs.main.adoc b/docs/attrs.main.adoc
@@ -0,0 +1,7 @@
+:icons: image
+:iconsdir: ../icons
+:imagesdir: ../figures
+:toc: macro
+:title-logo-image: image:neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
+// Uncomment next line to set page size (default is A4)
+//:pdf-page-size: Letter
diff --git a/docs/datasheet/index.adoc b/docs/datasheet/index.adoc
@@ -1,18 +1,9 @@
 = The NEORV32 RISC-V Processor: Datasheet
+include::../attrs.adoc[]
 :title: [Datasheet] The NEORV32 RISC-V Processor
-:author: Dipl.-Ing. Stephan Nolting
-:email: [email protected]
-:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
-:revnumber: v1.5.6.0
-:doctype: book
-:sectnums:
 :icons: font
 :imagesdir: img
-:stem:
-:reproducible:
-:listing-caption: Listing
 :toc: left
-:toclevels: 4
 :title-logo-image: neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
 :favicon: img/icon.png
 

diff --git a/docs/datasheet/main.adoc b/docs/datasheet/main.adoc
@@ -1,21 +1,6 @@
 = The NEORV32 RISC-V Processor: Datasheet
-:author: Dipl.-Ing. Stephan Nolting
-:email: [email protected]
-:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
-:revnumber: v1.5.6.0
-:doctype: book
-:sectnums:
-:icons: image
-:iconsdir: ../icons
-:imagesdir: ../figures
-:stem:
-:reproducible:
-:listing-caption: Listing
-:toc: macro
-:toclevels: 4
-:title-logo-image: image:neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
-// Uncomment next line to set page size (default is A4)
-//:pdf-page-size: Letter
+include::../attrs.adoc[]
+include::../attrs.main.adoc[]
 
 
 <<<

diff --git a/docs/userguide/index.adoc b/docs/userguide/index.adoc
@@ -1,18 +1,9 @@
 = The NEORV32 RISC-V Processor: User Guide
+include::../attrs.adoc[]
 :title: [User Guide] The NEORV32 RISC-V Processor
-:author: Dipl.-Ing. Stephan Nolting
-:email: [email protected]
-:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
-:revnumber: v1.5.6.0
-:doctype: book
-:sectnums:
 :icons: font
 :imagesdir: ../img
-:stem:
-:reproducible:
-:listing-caption: Listing
 :toc: left
-:toclevels: 4
 :title-logo-image: neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
 :favicon: ../img/icon.png
 

diff --git a/docs/userguide/main.adoc b/docs/userguide/main.adoc
@@ -1,21 +1,6 @@
 = The NEORV32 RISC-V Processor: User Guide
-:author: Dipl.-Ing. Stephan Nolting
-:email: [email protected]
-:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
-:revnumber: v1.5.6.0
-:doctype: book
-:sectnums:
-:icons: image
-:iconsdir: ../icons
-:imagesdir: ../figures
-:stem:
-:reproducible:
-:listing-caption: Listing
-:toc: macro
-:toclevels: 4
-:title-logo-image: image:neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
-// Uncomment next line to set page size (default is A4)
-//:pdf-page-size: Letter
+include::../attrs.adoc[]
+include::../attrs.main.adoc[]
 
 
 <<<