[rtl] Optimize UART RTS behavior (#433)

stnolting · Oct 21, 2022 · 24e884e · 24e884e
2 parents 7cf7eff + 78ad692
commit 24e884e
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Showing 4 changed files with 10 additions and 7 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -32,6 +32,7 @@ mimpid = 0x01040312 => Version 01.04.03.12 => v1.4.3.12
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 19.10.2022 | 1.7.7.4 | optimize UART's `RTS` (hardware flow control) behavior; [#433](https://github.com/stnolting/neorv32/pull/433) |
 | 15.10.2022 | 1.7.7.3 | :bug: fix bug in `is_power_of_two_f` VHDL function (thanks Alan!); [#482](https://github.com/stnolting/neorv32/pull/428) |
 | 12.10.2022 | 1.7.7.2 | add dedicated hardware reset to _all_ CPU counters (`[m]cycle[h]`, `[m]instret[h]`, `[m]hpmcounter[h]`); :sparkles: **all CSRs now provide a dedicated hardware reset**; [#426](https://github.com/stnolting/neorv32/pull/426) |
 | 09.10.2022 | 1.7.7.1 | fix Quartus synthesis issue (VHDL): make sure reset state is the _first_ entry in a state list [#423](https://github.com/stnolting/neorv32/pull/423) |

diff --git a/docs/datasheet/soc_uart.adoc b/docs/datasheet/soc_uart.adoc
@@ -90,10 +90,12 @@ UART0 supports optional hardware flow control using the standard CTS (clear to s
 / ready to receive "RTR") signals. Both hardware control flow mechanisms can be enabled individually.
 
 * If **RTS hardware flow control** is enabled by setting the _UART_CTRL_RTS_EN_ control register flag, the UART
-will pull the `uart0_rts_o` signal low if the UART's receiver is ready to receive new data.
-As long as this signal is low the connected device can send new data. `uart0_rts_o` is always LOW if the UART is disabled.
-The RTS line is de-asserted (going high) as soon as the start bit of a new incoming char has been
-detected.
+will drive the `uart0_rts_o` signal low if the UART RX FIFO is less than half full. As long as this signal is low,
+the connected device can send new data. `uart0_rts_o` is always low if the UART is disabled.
+
+[WARNING]
+If the _UART0_RX_FIFO_ configuration generic is set to it's minimum (=1), the RTS signal already goes low
+when a single character has been received by the UART that has not yet been read by the software.
 
 * If **CTS hardware flow control** is enabled by setting the _UART_CTRL_CTS_EN_ control register flag, the UART's
 transmitter will not start sending a new data until the `uart0_cts_i` signal goes low. During this time, the UART busy flag

diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -58,7 +58,7 @@ package neorv32_package is
 
   -- Architecture Constants (do not modify!) ------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070703"; -- NEORV32 version - no touchy!
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070704"; -- NEORV32 version - no touchy!
   constant archid_c     : natural := 19; -- official RISC-V architecture ID - hands off!
 
   -- Check if we're inside the Matrix -------------------------------------------------------

diff --git a/rtl/core/neorv32_uart.vhd b/rtl/core/neorv32_uart.vhd
@@ -502,8 +502,8 @@ begin
     end if;
   end process uart_rx_engine;
 
-  -- RX engine ready for a new char? --
-  rx_engine.rtr <= '1' when (rx_engine.state = S_RX_IDLE) and (ctrl(ctrl_en_c) = '1') else '0';
+  -- Enough space (incl. safety margin) in RX buffer for a new char (FIFO less than half-full)? --
+  rx_engine.rtr <= '1' when (rx_buffer.half = '0') and (ctrl(ctrl_en_c) = '1') else '0';
 
 
   -- RX FIFO --------------------------------------------------------------------------------