feat: patches uses a map in some cases #1626
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See [this sheet for the data from take_patches.rs](https://docs.google.com/spreadsheets/d/1D9vBZ1QJ6mwcIvV5wIL0hjGgVchcEnAyhvitqWu2ugU). I'm on an M3 Max with 96 GiB of RAM with macOS 14.4. This threshold likely depends on the ISA. Intuitively, repeated searching is `O(N_INDICES * lg N_PATCHES)` and repeated map lookups is `O(N_INDICES + N_PATCHES)`. It seems to me that the compiler & CPU would have trouble paralleling search (via SIMD or ILP) because of the branching, whereas map lookups are more obviously parallelized (e.g. SIMD hash computation). I'm not entirely sure why the cross over point seems to be around N_PATCHES / N_INDICES = 5. I believe the M3 Max has 128-bit registers, so if the indices are 32-bits then index arithmetic could be 4-way parallel.
lwwmanning
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This reverts commit 0b93fe0.
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danking
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A second attempt at #1626 with fixes from #1628 as well as the transition of ALPRD and SparseArray to use Patches. --- See [this sheet for the data from take_patches.rs](https://docs.google.com/spreadsheets/d/1D9vBZ1QJ6mwcIvV5wIL0hjGgVchcEnAyhvitqWu2ugU). I'm on an M3 Max with 96 GiB of RAM with macOS 14.4. This threshold likely depends on the ISA. Intuitively, repeated searching is `O(N_INDICES * lg N_PATCHES)` and repeated map lookups is `O(N_INDICES + N_PATCHES)`. It seems to me that the compiler & CPU would have trouble paralleling search (via SIMD or ILP) because of the branching, whereas map lookups are more obviously parallelized (e.g. SIMD hash computation). I'm not entirely sure why the cross over point seems to be around N_PATCHES / N_INDICES = 5. I believe the M3 Max has 128-bit registers, so if the indices are 32-bits then index arithmetic could be 4-way parallel.
danking
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Dec 10, 2024
A second attempt at #1626 with fixes from #1628 as well as the transition of ALPRD and SparseArray to use Patches. --- See [this sheet for the data from take_patches.rs](https://docs.google.com/spreadsheets/d/1D9vBZ1QJ6mwcIvV5wIL0hjGgVchcEnAyhvitqWu2ugU). I'm on an M3 Max with 96 GiB of RAM with macOS 14.4. This threshold likely depends on the ISA. Intuitively, repeated searching is `O(N_INDICES * lg N_PATCHES)` and repeated map lookups is `O(N_INDICES + N_PATCHES)`. It seems to me that the compiler & CPU would have trouble paralleling search (via SIMD or ILP) because of the branching, whereas map lookups are more obviously parallelized (e.g. SIMD hash computation). I'm not entirely sure why the cross over point seems to be around N_PATCHES / N_INDICES = 5. I believe the M3 Max has 128-bit registers, so if the indices are 32-bits then index arithmetic could be 4-way parallel.
danking
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Dec 11, 2024
A second attempt at #1626 with fixes from #1628 as well as the transition of ALPRD and SparseArray to use Patches. --- See [this sheet for the data from take_patches.rs] https://docs.google.com/spreadsheets/d/1D9vBZ1QJ6mwcIvV5wIL0hjGgVchcEnAyhvitqWu2ugU). I'm on an M3 Max with 96 GiB of RAM with macOS 14.4. This threshold likely depends on the ISA. Intuitively, repeated searching is `O(N_INDICES * lg N_PATCHES)` and repeated map lookups is `O(N_INDICES + N_PATCHES)`. It seems to me that the compiler & CPU would have trouble paralleling search (via SIMD or ILP) because of the branching, whereas map lookups are more obviously parallelized (e.g. SIMD hash computation). I'm not entirely sure why the cross over point seems to be around N_PATCHES / N_INDICES = 5. I believe the M3 Max has 128-bit registers, so if the indices are 32-bits then index arithmetic could be 4-way parallel.
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See this sheet for the data from take_patches.rs. I'm on an M3 Max with 96 GiB of RAM with macOS 14.4. This threshold likely depends on the ISA.
Intuitively, repeated searching is
O(N_INDICES * lg N_PATCHES)and repeated map lookups isO(N_INDICES + N_PATCHES). It seems to me that the compiler & CPU would have trouble paralleling search (via SIMD or ILP) because of the branching, whereas map lookups are more obviously parallelized (e.g. SIMD hash computation). I'm not entirely sure why the cross over point seems to be around N_PATCHES / N_INDICES = 5. I believe the M3 Max has 128-bit registers, so if the indices are 32-bits then index arithmetic could be 4-way parallel.