Debug features for Rust + verilator

README.md

@@ -27,6 +27,8 @@ Verilator simulations can be invoked from the repository root with
 make verilate simv TEST=<name of test, e.g. 'uart_sanity'>
 # Rust
 make verilate simv RUST=1 TEST_DIR=examples/hello_rt TEST=<name of test, e.g. 'uart'>
+# Rust (debug mode with software assertions)
+make verilate simv RUST=1 DEBUG=1 TEST_DIR=examples/hello_rt TEST=<name of test, e.g. 'uart'>
 ```
 
 This will clean and compile the design and the software test, then invoke the simulation.

examples/atalanta_bsp/src/timer_group.rs

@@ -63,6 +63,12 @@ impl Timer {
     /// Set current timer counter value
     #[inline]
     pub fn set_counter(&mut self, cnt: u32) {
+        #[cfg(debug_assertions)]
+        {
+            // Counter must not be set to a value higher than compare
+            let cmp = read_u32p(unsafe { &mut (*self.0).cmp as *mut u32 });
+            debug_assert!(cnt <= cmp);
+        }
         write_u32p(unsafe { &mut (*self.0).cnt as *mut u32 }, cnt)
     }
 

examples/hello_rt/Makefile

@@ -1,4 +1,8 @@
+ifndef DEBUG
+MAYBE_RELEASE = --release
+endif
+
 # Build the entire program
 .PHONY: $(TEST)
 $(TEST):
-	cargo build --release -Frtl-tb --example $(TEST) $(CARGO_FLAGS)
+	cargo build $(MAYBE_RELEASE) -Frtl-tb --example $(TEST) $(CARGO_FLAGS)

examples/periodic_tasks/Makefile

@@ -1,4 +1,8 @@
+ifndef DEBUG
+MAYBE_RELEASE = --release
+endif
+
 # Build the entire program
 .PHONY: $(TEST)
 $(TEST):
-	cargo build --release -Frtl-tb --bin $(TEST) $(CARGO_FLAGS)
+	cargo build $(MAYBE_RELEASE) -Frtl-tb --bin $(TEST) $(CARGO_FLAGS)