-
Notifications
You must be signed in to change notification settings - Fork 2
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
[SW] change periodic tasks to fixed cycle counts #85
Conversation
Please run Consider also turning on auto-formatting for this workspace by adding to .vscode/settings.json: |
Merge will not be clean due to updated Timer API. I propose rebasing onto latest main; we can look at it together if you haven't done it before. EDIT: I do recommend to get this working functionally perfect, before considering the rebase -- that will be the last thing to do before merge. |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I got the idea. Seems functionally correct which is great. I propose you implement changes to improve readability as requested and submit for re-review. Then let me know and I can do the rebase, or we can do it together if you'd like to learn about that.
examples/periodic_tasks/src/main.rs
Outdated
@@ -10,7 +10,7 @@ use bsp::{ | |||
embedded_io::Write, | |||
mtimer::{self, MTimer}, | |||
nested_interrupt, | |||
riscv::{self, asm::wfi}, | |||
riscv::{self, asm::{self, nop, wfi}, read_csr, register::{cycle, mcounteren}}, |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Some of these are unused. The linter should underline them in yellow. Please remove unused imports.
examples/periodic_tasks/src/main.rs
Outdated
// TODO: figure out bsp access to CSRs | ||
let mut cycle_lo: u32; | ||
let mut cycle_hi: u32; | ||
let mut retired_lo: u32; | ||
let mut retired_hi: u32; | ||
core::arch::asm!("csrr {0}, 0xB00", out(reg) cycle_lo); | ||
core::arch::asm!("csrr {0}, 0xB80", out(reg) cycle_hi); | ||
core::arch::asm!("csrr {0}, 0xB02", out(reg) retired_lo); | ||
core::arch::asm!("csrr {0}, 0xB82", out(reg) retired_hi); | ||
sprintln!("cycles: {}{}", cycle_hi, cycle_lo ); | ||
sprintln!("instrs: {}{}", retired_hi, retired_lo ); |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Here you go:
// Read top & bottom halves into one 64-bit binding:
let cycle = riscv::register::cycle::read64();
// Read halves separately
let cycle_lo = riscv::register::cycle::read();
let cycle_hi = riscv::register::cycleh::read();
// For "retired", same as above but `minstret`
let minstret = riscv::register::minstret::read64();
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
With latest main, same can be achieved slightly more idiomatically via bsp::register::cycle::read64
, etc., but you shouldn't care about that. Just use the above code.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
The example code (both versions) cause an illegal instruction, need to debug.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
mcycle
, not cycle
(which is supervisor variant)
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
To assert that the test doesn't break by changes to periph_clk_div, I propose you adjust the start of main as follows:
#[entry]
fn main() -> ! {
// Assert that periph clk div is as configured
write_u32(CFG_BASE + PERIPH_CLK_DIV_OFS, PERIPH_CLK_DIV);
let mut serial = ApbUart::init(CPU_FREQ, 115_200);
sprintln!("[periodic_tasks (PCS={:?})]", cfg!(feature = "pcs"));
sprintln!(
"PERIPH_CLK_DIV: {}",
read_u32(CFG_BASE + PERIPH_CLK_DIV_OFS)
);
Also change PERIPH_CLK_DIV to u32 (which is it's native representation) then cast as necessary.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Task duration saturates to zero due to division. Precision must be increased from us to ns.
Fixes the problem with value saturation.
Fixed by the latest commit. |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Seems functionally correct :D maybe for real this time. There's at least the periph clk div issue which is critical, rest is style & re-enabling code, I think. I can adopt the branch after this round.
examples/periodic_tasks/src/main.rs
Outdated
// TODO: figure out bsp access to CSRs | ||
let mut cycle_lo: u32; | ||
let mut cycle_hi: u32; | ||
let mut retired_lo: u32; | ||
let mut retired_hi: u32; | ||
core::arch::asm!("csrr {0}, 0xB00", out(reg) cycle_lo); | ||
core::arch::asm!("csrr {0}, 0xB80", out(reg) cycle_hi); | ||
core::arch::asm!("csrr {0}, 0xB02", out(reg) retired_lo); | ||
core::arch::asm!("csrr {0}, 0xB82", out(reg) retired_hi); | ||
sprintln!("cycles: {}{}", cycle_hi, cycle_lo ); | ||
sprintln!("instrs: {}{}", retired_hi, retired_lo ); |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
mcycle
, not cycle
(which is supervisor variant)
examples/periodic_tasks/src/main.rs
Outdated
let total_in_task0 = TASK0.duration_ns * TASK0_COUNT as u32; | ||
let total_in_task1 = TASK1.duration_ns * TASK1_COUNT as u32; | ||
let total_in_task2 = TASK2.duration_ns * TASK2_COUNT as u32; | ||
let total_in_task3 = TASK3.duration_ns * TASK3_COUNT as u32; |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
tbh best to rename these to total_ns_in_task0
, etc.
examples/periodic_tasks/src/main.rs
Outdated
total_in_task0, | ||
total_in_task1, | ||
total_in_task2, | ||
total_in_task3, | ||
total_in_task0 + total_in_task1 + total_in_task2 + total_in_task3, | ||
); | ||
|
||
/* TODO: reintroduce after mtimer div fixed |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Yep. I think for now it should be OK to just change the const PERIPH_CLK_DIV: u32 = 2;
to 1 from atalanta_bsp/src/mtimer.rs
and atalanta_bsp/src/timer_group.rs
. Then re-introduce these.
Should be all good now, @hegza please merge. |
6b24aa0
to
3c084a7
Compare
This makes them take the expected amount of time.
Plus update rt-ibex reference.
Need to clean up before merging, but creating this already as the produced results are likely final.