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[SW] change periodic tasks to fixed cycle counts #85

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merged 29 commits into from
Feb 21, 2025
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ANurmi
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@ANurmi ANurmi commented Feb 19, 2025

Plus update rt-ibex reference.
Need to clean up before merging, but creating this already as the produced results are likely final.

@ANurmi ANurmi requested a review from hegza February 19, 2025 10:41
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hegza commented Feb 19, 2025

Please run cargo fmt from examples/periodic_tasks directory.

Consider also turning on auto-formatting for this workspace by adding to .vscode/settings.json: "editor.formatOnSave": true. This should reduce the amount of back-and-forth changes with subsequent git commits as every commit produces standard format. Be mindful that this VSCode option is a little dangerous for a project that does not use a standard formatting policy as it can clutter your git, so consider making it so that it only applies to this software workspace.

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hegza commented Feb 19, 2025

Merge will not be clean due to updated Timer API. I propose rebasing onto latest main; we can look at it together if you haven't done it before.

EDIT: I do recommend to get this working functionally perfect, before considering the rebase -- that will be the last thing to do before merge.

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I got the idea. Seems functionally correct which is great. I propose you implement changes to improve readability as requested and submit for re-review. Then let me know and I can do the rebase, or we can do it together if you'd like to learn about that.

@@ -10,7 +10,7 @@ use bsp::{
embedded_io::Write,
mtimer::{self, MTimer},
nested_interrupt,
riscv::{self, asm::wfi},
riscv::{self, asm::{self, nop, wfi}, read_csr, register::{cycle, mcounteren}},
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Some of these are unused. The linter should underline them in yellow. Please remove unused imports.

Comment on lines 194 to 204
// TODO: figure out bsp access to CSRs
let mut cycle_lo: u32;
let mut cycle_hi: u32;
let mut retired_lo: u32;
let mut retired_hi: u32;
core::arch::asm!("csrr {0}, 0xB00", out(reg) cycle_lo);
core::arch::asm!("csrr {0}, 0xB80", out(reg) cycle_hi);
core::arch::asm!("csrr {0}, 0xB02", out(reg) retired_lo);
core::arch::asm!("csrr {0}, 0xB82", out(reg) retired_hi);
sprintln!("cycles: {}{}", cycle_hi, cycle_lo );
sprintln!("instrs: {}{}", retired_hi, retired_lo );
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Here you go:

// Read top & bottom halves into one 64-bit binding:
let cycle = riscv::register::cycle::read64();

// Read halves separately
let cycle_lo = riscv::register::cycle::read();
let cycle_hi = riscv::register::cycleh::read();

// For "retired", same as above but `minstret`
let minstret = riscv::register::minstret::read64();

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With latest main, same can be achieved slightly more idiomatically via bsp::register::cycle::read64, etc., but you shouldn't care about that. Just use the above code.

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The example code (both versions) cause an illegal instruction, need to debug.

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mcycle, not cycle (which is supervisor variant)

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To assert that the test doesn't break by changes to periph_clk_div, I propose you adjust the start of main as follows:

#[entry]
fn main() -> ! {
    // Assert that periph clk div is as configured
    write_u32(CFG_BASE + PERIPH_CLK_DIV_OFS, PERIPH_CLK_DIV);

    let mut serial = ApbUart::init(CPU_FREQ, 115_200);
    sprintln!("[periodic_tasks (PCS={:?})]", cfg!(feature = "pcs"));
    sprintln!(
        "PERIPH_CLK_DIV: {}",
        read_u32(CFG_BASE + PERIPH_CLK_DIV_OFS)
    );

Also change PERIPH_CLK_DIV to u32 (which is it's native representation) then cast as necessary.

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Task duration saturates to zero due to division. Precision must be increased from us to ns.

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hegza commented Feb 19, 2025

Task duration saturates to zero due to division. Precision must be increased from us to ns.

Fixed by the latest commit.

@ANurmi ANurmi marked this pull request as ready for review February 20, 2025 13:44
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Seems functionally correct :D maybe for real this time. There's at least the periph clk div issue which is critical, rest is style & re-enabling code, I think. I can adopt the branch after this round.

Comment on lines 194 to 204
// TODO: figure out bsp access to CSRs
let mut cycle_lo: u32;
let mut cycle_hi: u32;
let mut retired_lo: u32;
let mut retired_hi: u32;
core::arch::asm!("csrr {0}, 0xB00", out(reg) cycle_lo);
core::arch::asm!("csrr {0}, 0xB80", out(reg) cycle_hi);
core::arch::asm!("csrr {0}, 0xB02", out(reg) retired_lo);
core::arch::asm!("csrr {0}, 0xB82", out(reg) retired_hi);
sprintln!("cycles: {}{}", cycle_hi, cycle_lo );
sprintln!("instrs: {}{}", retired_hi, retired_lo );
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mcycle, not cycle (which is supervisor variant)

Comment on lines 207 to 210
let total_in_task0 = TASK0.duration_ns * TASK0_COUNT as u32;
let total_in_task1 = TASK1.duration_ns * TASK1_COUNT as u32;
let total_in_task2 = TASK2.duration_ns * TASK2_COUNT as u32;
let total_in_task3 = TASK3.duration_ns * TASK3_COUNT as u32;
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tbh best to rename these to total_ns_in_task0, etc.

total_in_task0,
total_in_task1,
total_in_task2,
total_in_task3,
total_in_task0 + total_in_task1 + total_in_task2 + total_in_task3,
);

/* TODO: reintroduce after mtimer div fixed
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Yep. I think for now it should be OK to just change the const PERIPH_CLK_DIV: u32 = 2; to 1 from atalanta_bsp/src/mtimer.rs and atalanta_bsp/src/timer_group.rs. Then re-introduce these.

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ANurmi commented Feb 21, 2025

Should be all good now, @hegza please merge.

@hegza hegza merged commit 8aab319 into main Feb 21, 2025
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@hegza hegza deleted the sw/fixed-tasks branch February 21, 2025 13:25
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3 participants