AnTiQ

A hardware priority queue with constant response time written in SystemVerilog.

Requirements

• Mentor Questa/Modelsim is used for RTL simulation. Simulation instructions at ./sim/README.md.
• Xilinx Vivado is required for FPGA implementations.

Contributing

Contributions to the repository are welcome and appreciated.

• For bug reporting, please use GitHub issues.
• For completed bug fixes and repository improvements such as testbench expansion, please create a pull request.
• Significant modifications to the behaviour or scope of the design are recommended to be forked to separate repositories.

References

When using this design in your reseach, please cite the following publication:

@INPROCEEDINGS{AnTiQ,
  author={Nurmi, Antti and Lindgren, Per and Szymkowiak, Tom and Hämäläinen, Timo D.},
  booktitle={2023 26th Euromicro Conference on Digital System Design (DSD)}, 
  title={AnTiQ: A Hardware-Accelerated Priority Queue Design with Constant Time Arbitrary Element Removal}, 
  year={2023},
  volume={},
  number={},
  pages={462-469},
  doi={10.1109/DSD60849.2023.00070}
}