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Revert "[RISCV] Teach RISCVMergeBaseOffset to handle inline asm" #19

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Revert "[RISCV] Teach RISCVMergeBaseOffset to handle inline asm" #19

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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -237,7 +237,7 @@ bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
// RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand).
if (!AddrReg.isReg())
return true;
if (!Offset.isImm() && !Offset.isGlobal() && !Offset.isMCSymbol())
if (!Offset.isImm() && !Offset.isGlobal())
return true;

MCOperand MCO;
Expand All @@ -246,7 +246,7 @@ bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,

if (Offset.isImm())
OS << MCO.getImm();
else if (Offset.isGlobal() || Offset.isMCSymbol())
else if (Offset.isGlobal())
OS << *MCO.getExpr();
OS << "(" << RISCVInstPrinter::getRegisterName(AddrReg.getReg()) << ")";
return false;
Expand Down
69 changes: 5 additions & 64 deletions llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -357,8 +357,6 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
// Tail: lw vreg3, 8(vreg2)

std::optional<int64_t> CommonOffset;
DenseMap<const MachineInstr *, SmallVector<unsigned>>
InlineAsmMemoryOpIndexesMap;
for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) {
switch (UseMI.getOpcode()) {
default:
Expand Down Expand Up @@ -393,44 +391,6 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
if (CommonOffset && Offset != CommonOffset)
return false;
CommonOffset = Offset;
break;
}
case RISCV::INLINEASM:
case RISCV::INLINEASM_BR: {
SmallVector<unsigned> InlineAsmMemoryOpIndexes;
unsigned NumOps = 0;
for (unsigned I = InlineAsm::MIOp_FirstOperand;
I < UseMI.getNumOperands(); I += 1 + NumOps) {
const MachineOperand &FlagsMO = UseMI.getOperand(I);
// Should be an imm.
if (!FlagsMO.isImm())
continue;

unsigned Flags = FlagsMO.getImm();
NumOps = InlineAsm::getNumOperandRegisters(Flags);

// Memory constraints have two operands.
if (NumOps != 2 || !InlineAsm::isMemKind(Flags))
continue;

const MachineOperand &AddrMO = UseMI.getOperand(I + 1);
if (!AddrMO.isReg() || AddrMO.getReg() != DestReg)
continue;

const MachineOperand &OffsetMO = UseMI.getOperand(I + 2);
if (!OffsetMO.isImm())
continue;

// All inline asm memory operands must use the same offset.
int64_t Offset = OffsetMO.getImm();
if (CommonOffset && Offset != CommonOffset)
return false;
CommonOffset = Offset;
InlineAsmMemoryOpIndexes.push_back(I + 1);
}
InlineAsmMemoryOpIndexesMap.insert(
std::make_pair(&UseMI, InlineAsmMemoryOpIndexes));
break;
}
}
}
Expand All @@ -455,32 +415,13 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
// Update the immediate in the load/store instructions to add the offset.
for (MachineInstr &UseMI :
llvm::make_early_inc_range(MRI->use_instructions(DestReg))) {
if (UseMI.getOpcode() == RISCV::INLINEASM ||
UseMI.getOpcode() == RISCV::INLINEASM_BR) {
auto &InlineAsmMemoryOpIndexes = InlineAsmMemoryOpIndexesMap[&UseMI];
for (unsigned I : InlineAsmMemoryOpIndexes) {
MachineOperand &MO = UseMI.getOperand(I + 1);
switch (ImmOp.getType()) {
case MachineOperand::MO_GlobalAddress:
MO.ChangeToGA(ImmOp.getGlobal(), ImmOp.getOffset(),
ImmOp.getTargetFlags());
break;
case llvm::MachineOperand::MachineOperandType::MO_MCSymbol:
MO.ChangeToMCSymbol(ImmOp.getMCSymbol(), ImmOp.getTargetFlags());
MO.setOffset(ImmOp.getOffset());
break;
default:
report_fatal_error("unsupported machine operand type");
break;
}
}
} else {
UseMI.removeOperand(2);
UseMI.addOperand(ImmOp);
}
UseMI.removeOperand(2);
UseMI.addOperand(ImmOp);
// Update the base reg in the Tail instruction to feed from LUI.
// Output of Hi is only used in Lo, no need to use MRI->replaceRegWith().
UseMI.getOperand(1).setReg(Hi.getOperand(0).getReg());
}

MRI->replaceRegWith(Lo.getOperand(0).getReg(), Hi.getOperand(0).getReg());
Lo.eraseFromParent();
return true;
}
Expand Down
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