add full flag detection; do not interfere with data-flow

slaclab · Oct 31, 2023 · e4fc31c · e4fc31c
1 parent dfbd2f6
commit e4fc31c
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Showing 4 changed files with 34 additions and 8 deletions.
diff --git a/protocols/ssp/rtl/SspDecoder12b14b.vhd b/protocols/ssp/rtl/SspDecoder12b14b.vhd
@@ -45,6 +45,7 @@ entity SspDecoder12b14b is
       sof            : out sl;
       eof            : out sl;
       eofe           : out sl;
+      fifoFull       : out sl;
       -- Decoder Monitoring
       idleCode       : out sl;
       validDec       : out sl;
@@ -97,8 +98,10 @@ begin
          SSP_IDLE_K_G         => "1",
          SSP_SOF_CODE_G       => K_120_0_C,
          SSP_SOF_K_G          => "1",
-         SSP_EOF_CODE_G       => K_120_2_C,
-         SSP_EOF_K_G          => "1")
+         SSP_EOF_CODE_G       => K_120_1_C,
+         SSP_EOF_K_G          => "1",
+         SSP_FULL_CODE_G      => K_120_2_C,
+         SSP_FULL_K_G         => "1")
       port map (
          -- Clock and Reset
          clk            => clk,
@@ -117,6 +120,7 @@ begin
          idle           => idleInt,
          sof            => sof,
          eof            => eof,
-         eofe           => eofe);
+         eofe           => eofe,
+         fifoFull       => fifoFull);
 
 end architecture rtl;
diff --git a/protocols/ssp/rtl/SspDeframer.vhd b/protocols/ssp/rtl/SspDeframer.vhd
@@ -36,7 +36,9 @@ entity SspDeframer is
       SSP_SOF_CODE_G       : slv;
       SSP_SOF_K_G          : slv;
       SSP_EOF_CODE_G       : slv;
-      SSP_EOF_K_G          : slv);
+      SSP_EOF_K_G          : slv;
+      SSP_FULL_CODE_G      : slv;
+      SSP_FULL_K_G         : slv);
    port (
       -- Clock and Reset
       clk            : in  sl;
@@ -55,7 +57,8 @@ entity SspDeframer is
       idle           : out sl;
       sof            : out sl;
       eof            : out sl;
-      eofe           : out sl);
+      eofe           : out sl;
+      fifoFull       : out sl);
 end entity SspDeframer;
 
 architecture rtl of SspDeframer is
@@ -81,6 +84,7 @@ architecture rtl of SspDeframer is
       sof      : sl;
       eof      : sl;
       eofe     : sl;
+      full     : sl;
 
    end record RegType;
 
@@ -97,7 +101,8 @@ architecture rtl of SspDeframer is
       idle      => '0',
       sof       => '0',
       eof       => '0',
-      eofe      => '0');
+      eofe      => '0',
+      full      => '0');
 
    signal r   : RegType := REG_INIT_C;
    signal rin : RegType;
@@ -111,8 +116,19 @@ begin
 
       v.errorOut := '0';
 
+      -- reset the full strobe
+      v.full     := '0';
+
       if (validIn = '1') then
 
+         -- simple raise of Full flag for now
+         if (dataKIn = SSP_FULL_K_G) and (dataIn = SSP_FULL_CODE_G) then
+            v.full := '1';
+         else
+            v.full := '0';
+         end if;
+
+
          if (dataKIn = SSP_IDLE_K_G) and (dataIn = SSP_IDLE_CODE_G) then
             v.idle := '1';
          else

diff --git a/protocols/ssp/rtl/SspLowSpeedDecoder12b14bWrapper.vhd b/protocols/ssp/rtl/SspLowSpeedDecoder12b14bWrapper.vhd
@@ -41,6 +41,7 @@ entity SspLowSpeedDecoder12b14bWrapper is
       rxSof           : out slv(NUM_LANE_G-1 downto 0);
       rxEof           : out slv(NUM_LANE_G-1 downto 0);
       rxEofe          : out slv(NUM_LANE_G-1 downto 0);
+      rxFifoFull      : out slv(NUM_LANE_G-1 downto 0);
       -- AXI-Lite Interface (axilClk domain)
       axilClk         : in  sl;
       axilRst         : in  sl;
@@ -113,7 +114,8 @@ begin
             rxData         => rxData(i),
             rxSof          => rxSof(i),
             rxEof          => rxEof(i),
-            rxEofe         => rxEofe(i));
+            rxEofe         => rxEofe(i),
+            rxFifoFull     => rxFifoFull(i));
 
    end generate GEN_VEC;
 

diff --git a/protocols/ssp/rtl/SspLowSpeedDecoderLane.vhd b/protocols/ssp/rtl/SspLowSpeedDecoderLane.vhd
@@ -55,7 +55,8 @@ entity SspLowSpeedDecoderLane is
       rxData         : out slv(DATA_WIDTH_G-1 downto 0);
       rxSof          : out sl;
       rxEof          : out sl;
-      rxEofe         : out sl);
+      rxEofe         : out sl;
+      rxFifoFull     : out slv(NUM_LANE_G-1 downto 0));
 end SspLowSpeedDecoderLane;
 
 architecture mapping of SspLowSpeedDecoderLane is
@@ -176,6 +177,7 @@ begin
    end process;
 
    GEN_10B12B : if (DATA_WIDTH_G = 10) generate
+      rxFifoFull <= '0';
       U_Decoder : entity surf.SspDecoder10b12b
          generic map (
             TPD_G          => TPD_G,
@@ -224,6 +226,7 @@ begin
             sof            => rxSof,
             eof            => rxEof,
             eofe           => rxEofe,
+            fifoFull       => rxFifoFull,
             -- Decoder Monitoring
             idleCode       => idle,
             validDec       => decodeValid,
@@ -232,6 +235,7 @@ begin
    end generate;
 
    GEN_16B20B : if (DATA_WIDTH_G = 16) generate
+      rxFifoFull <= '0';
       U_Decoder : entity surf.SspDecoder8b10b
          generic map (
             TPD_G          => TPD_G,