switch to 78.125MHz for DRP clock; revert reset modifications

slaclab · Oct 4, 2024 · 9bcedb9 · 9bcedb9
2 parents 3033857 + 31f2bda
commit 9bcedb9
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Showing 4 changed files with 11 additions and 12 deletions.
diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp
diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci
@@ -183,7 +183,7 @@
         "TXPROGDIV_FREQ_SOURCE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "TXPROGDIV_FREQ_VAL": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
         "SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "FREERUN_FREQUENCY": [ { "value": "92.857", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "FREERUN_FREQUENCY": [ { "value": "78.125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -734,7 +734,7 @@
         "C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_CPLL_VCO_FREQUENCY": [ { "value": "3714.2857", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_FORCE_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_FREERUN_FREQUENCY": [ { "value": "92.857", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_FREERUN_FREQUENCY": [ { "value": "78.125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_GT_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_GT_REV": [ { "value": "67", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],

diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd
@@ -35,8 +35,6 @@ entity Pgp2fcGtyCoreWrapper is
       AXI_CLK_FREQ_G      : real             := 125.0e6;
       AXI_BASE_ADDR_G     : slv(31 downto 0) := (others => '0'));
    port (
-      -- Could use gtUserRefClk instead of stableClk
-      -- Then change stableRst to extRst
       stableClk      : in  sl;
       stableRst      : in  sl;
 
@@ -449,8 +447,8 @@ begin
 
    cPllRefClkSel     <= ite(SEL_FABRIC_REFCLK_G, "111", "001");
 
-   rstSyncRxIn       <= rxResetAlignCheck;
-   rxResetGt         <= rxResetAlignCheck;
+   rstSyncRxIn       <= rxResetAlignCheck or rxReset;
+   rxResetGt         <= rxResetAlignCheck or rxReset;
 
    txOutClk          <= txOutClkB;
    rxOutClk          <= rxOutClkB;

diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd
@@ -115,10 +115,11 @@ begin
 
    pgpTxResetDone <= phyTxReady;
 
+   -- assuming a 78.125MHz stableClk
    U_RstSync_1 : entity surf.PwrUpRst
       generic map (
          TPD_G      => TPD_G,
-         DURATION_G => ite(SIMULATION_G, 12500, 125000000))  -- 100us in sim; 1s in silicon
+         DURATION_G => ite(SIMULATION_G, 7813, 78130000))  -- 100us in sim; 1s in silicon
       port map (
          arst   => pgpTxIn.resetGt,                          -- [in]
          clk    => stableClk,                                -- [in]
@@ -129,7 +130,7 @@ begin
    U_RstSync_4 : entity surf.SynchronizerOneShot
       generic map (
          TPD_G         => TPD_G,
-         PULSE_WIDTH_G => 12500)  -- 100us in sim and silicon; otherwise it takes forever to lock
+         PULSE_WIDTH_G => ite(SIMULATION_G, 7813, 78130000))  -- 100us in sim; 1s in silicon
       port map (
          clk     => stableClk,                                  -- [in]
          dataIn  => phyRxInit,                                  -- [in]
@@ -139,7 +140,7 @@ begin
    U_RstSync_2 : entity surf.PwrUpRst
       generic map (
          TPD_G      => TPD_G,
-         DURATION_G => ite(SIMULATION_G, 12500, 125000000))  -- 100us in sim; 1s in silicon
+         DURATION_G => ite(SIMULATION_G, 7813, 78130000))  -- 100us in sim; 1s in silicon
       port map (
          arst   => pgpRxIn.resetRx,                          -- [in]
          clk    => stableClk,                                -- [in]
@@ -150,7 +151,7 @@ begin
    U_RstSync_3 : entity surf.PwrUpRst
       generic map (
          TPD_G      => TPD_G,
-         DURATION_G => ite(SIMULATION_G, 12500, 125000000))  -- 100us in sim; 1s in silicon
+         DURATION_G => ite(SIMULATION_G, 7813, 78130000))  -- 100us in sim; 1s in silicon
       port map (
          arst   => pgpTxIn.resetTx,                          -- [in]
          clk    => stableClk,                                -- [in]