try recclk (prv rst scheme works)

slaclab · Oct 5, 2024 · 6670ba9 · 6670ba9
1 parent f7b14cd
commit 6670ba9
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Showing 4 changed files with 11 additions and 5 deletions.
diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp
diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci
@@ -155,7 +155,7 @@
         "RX_CC_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
         "RX_CC_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "RX_CC_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
-        "ENABLE_OPTIONAL_PORTS": [ { "value": "cplllockdetclk_in cplllocken_in cpllrefclksel_in drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in gtgrefclk_in loopback_in rxcdrreset_in rxpcsreset_in rxpmareset_in rxpolarity_in txpcsreset_in txpmareset_in txpolarity_in cpllfbclklost_out cplllock_out cpllrefclklost_out drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_OPTIONAL_PORTS": [ { "value": "cplllockdetclk_in cplllocken_in cpllrefclksel_in drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in gtgrefclk_in loopback_in rxcdrreset_in rxpcsreset_in rxpmareset_in rxpolarity_in txpcsreset_in txpmareset_in txpolarity_in cpllfbclklost_out cplllock_out cpllrefclklost_out drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxrecclkout_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "RX_REFCLK_SOURCE": [ { "value": "", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "TX_REFCLK_SOURCE": [ { "value": "", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "RX_RECCLK_OUTPUT": [ { "value": "", "resolve_type": "user", "usage": "all" } ],
@@ -170,7 +170,7 @@
         "PRESET": [ { "value": "GTY-Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "INTERNAL_PRESET": [ { "value": "Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
-        "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "25", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "26", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
         "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "7", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
         "INTERNAL_CHANNEL_COLUMN_LOC_MAX": [ { "value": "96", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
         "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
@@ -825,7 +825,7 @@
         "IPCONTEXT": [ { "value": "IP_Flow" } ],
         "IPREVISION": [ { "value": "18" } ],
         "MANAGED": [ { "value": "TRUE" } ],
-        "OUTPUTDIR": [ { "value": "../../../../FcHubBittware_project.gen/sources_1/ip/Pgp2fcGtyCore" } ],
+        "OUTPUTDIR": [ { "value": "." } ],
         "SELECTEDSIMMODEL": [ { "value": "" } ],
         "SHAREDDIR": [ { "value": "." } ],
         "SWVERSION": [ { "value": "2024.1" } ],
@@ -907,6 +907,7 @@
         "rxoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "rxphaligndone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "rxrecclkout_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "rxresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "rxsyncdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "txoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],

diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd
@@ -46,6 +46,7 @@ entity Pgp2fcGtyCoreWrapper is
       gtRxN          : in  sl;
       gtTxP          : out sl;
       gtTxN          : out sl;
+      gtRxRecClk     : out sl;
 
       -- Rx ports
       phyRxReady     : out sl;
@@ -159,6 +160,7 @@ architecture mapping of Pgp2fcGtyCoreWrapper is
          rxoutclk_out                       : out std_logic_vector (0 downto 0);
          rxphaligndone_out                  : out std_logic_vector (0 downto 0);
          rxpmaresetdone_out                 : out std_logic_vector (0 downto 0);
+         rxrecclkout_out                    : out std_logic_vector (0 downto 0);
          rxresetdone_out                    : out std_logic_vector (0 downto 0);
          rxsyncdone_out                     : out std_logic_vector (0 downto 0);
          txoutclk_out                       : out std_logic_vector (0 downto 0);
@@ -328,6 +330,7 @@ begin
          rxoutclk_out(0)                       => rxOutClkGt,
          txoutclk_out(0)                       => txOutClkGt, -- unused
          rxpmaresetdone_out(0)                 => rxPmaResetDoneInt,
+         rxrecclkout_out(0)                    => gtRxRecClk,
          rxresetdone_out(0)                    => rxResetDoneInt,
          rxsyncdone_out(0)                     => rxSyncDone,
          txpmaresetdone_out(0)                 => txPmaResetDone,

diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd
@@ -52,6 +52,7 @@ entity Pgp2fcGtyUltra is
       gtRefClk         : in  sl;
       gtFabricRefClk   : in  sl;
       gtUserRefClk     : in  sl;
+      gtRxRecClk       : out sl;
       -- Gt Serial IO
       pgpGtTxP         : out sl;
       pgpGtTxN         : out sl;
@@ -201,6 +202,7 @@ begin
          gtRefClk        => gtRefClk,
          gtFabricRefClk  => gtFabricRefClk,
          gtUserRefClk    => gtUserRefClk,
+         gtRxRecClk      => gtRxRecClk,
          gtRxP           => pgpGtRxP,
          gtRxN           => pgpGtRxN,
          gtTxP           => pgpGtTxP,