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adding triMode output port support for MDIO
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@ruck314
ruck314 committed Oct 23, 2024
1 parent ab93728 commit 5848e2c
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Showing 5 changed files with 90 additions and 82 deletions.
47 changes: 26 additions & 21 deletions devices/Ti/dp83867/core/SgmiiDp83867Mdio.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ entity SgmiiDp83867Mdio is
TPD_G : time := 1 ns;
-- half-period of MDC in clk cycles
DIV_G : natural range 1 to natural'high := 1;
PHY_G : natural range 0 to 31 := 3);
PHY_G : natural range 0 to 15 := 3);
port (
-- clock and reset
clk : in sl;
Expand All @@ -38,6 +38,7 @@ entity SgmiiDp83867Mdio is
linkIsUp : out sl;
-- MDIO interface
mdc : out sl;
mdTri : out sl;
mdo : out sl;
mdi : in sl;
-- link status change interrupt
Expand All @@ -47,25 +48,27 @@ end entity SgmiiDp83867Mdio;
architecture rtl of SgmiiDp83867Mdio is

constant P_INIT_C : MdioProgramArray := (
mdioWriteInst(PHY_G, 16#0D#, x"001F", false), -- Address 0x000D: Setup for extended address
mdioWriteInst(PHY_G, 16#0E#, x"00D3", false), -- Address 0x000E: Set extended address = 0x00D3
mdioWriteInst(PHY_G, 16#0D#, x"401F", false), -- Address 0x000D: Setup for extended data write
mdioWriteInst(PHY_G, 16#0E#, x"4000", false), -- Address 0x000E: Enable SGMII clock

mdioWriteInst(PHY_G, 16#0D#, x"001F", false), -- Address 0x000D: Setup for extended address
mdioWriteInst(PHY_G, 16#0E#, x"0032", false), -- Address 0x000E: Set extended address = 0x0032
mdioWriteInst(PHY_G, 16#0D#, x"401F", false), -- Address 0x000D: Setup for extended data write
mdioWriteInst(PHY_G, 16#0E#, x"0000", false), -- Address 0x000E: RGMII must be disabled

mdioWriteInst(PHY_G, 16#1E#, x"0082", false), -- Address 0x001E: INTN/PWDNN Pad is an Interrupt Output.
mdioWriteInst(PHY_G, 16#14#, x"29C7", false), -- Address 0x0014: Configure interrupt polarity, enable auto negotiation, Enable Speed Optimization
mdioWriteInst(PHY_G, 16#12#, X"0c00", false), -- Address 0x0012: Interrupt of link and autoneg changes
mdioWriteInst(PHY_G, 16#10#, x"5868", false), -- Address 0x0010: Enable SGMII
-- mdioWriteInst(PHY_G, 16#09#, X"0200", false), -- Address 0x0009: Advertise 1000 FD only
-- mdioWriteInst(PHY_G, 16#04#, X"0140", false), -- Address 0x0004: Advertise 10/100 FD only
mdioWriteInst(PHY_G, 16#00#, x"1140", false), -- Address 0x0000: Enable autoneg and full duplex

mdioWriteInst(PHY_G, 16#1F#, x"4000", true)); -- Address 0x001F: Initiate the soft restart.
mdioWriteInst(PHY_G, 16#0D#, x"001F", false), -- Address 0x0D: Setup for extended address
mdioWriteInst(PHY_G, 16#0E#, x"00D3", false), -- Address 0x0E: Set extended address = 0xD3 (more than 5-bit address)
mdioWriteInst(PHY_G, 16#0D#, x"401F", false), -- Address 0x0D: Setup for extended data write
mdioWriteInst(PHY_G, 16#0E#, x"4000", false), -- Address 0x0E: Enable SGMII clock

mdioWriteInst(PHY_G, 16#0D#, x"001F", false), -- Address 0x0D: Setup for extended address
mdioWriteInst(PHY_G, 16#0E#, x"0032", false), -- Address 0x0E: Set extended address = 0x32 (more than 5-bit address)
mdioWriteInst(PHY_G, 16#0D#, x"401F", false), -- Address 0x0D: Setup for extended data write
mdioWriteInst(PHY_G, 16#0E#, x"0000", false), -- Address 0x0E: RGMII must be disabled

mdioWriteInst(PHY_G, 16#1E#, x"0082", false), -- Address 0x1E: INTN/PWDNN Pad is an Interrupt Output.
mdioWriteInst(PHY_G, 16#14#, x"29C7", false), -- Address 0x14: Configure interrupt polarity, enable auto negotiation, Enable Speed Optimization
mdioWriteInst(PHY_G, 16#12#, X"0c00", false), -- Address 0x12: Interrupt of link and autoneg changes
mdioWriteInst(PHY_G, 16#10#, x"5848", false), -- Address 0x10: Enable SGMII

-- mdioWriteInst(PHY_G, 16#10#, x"5868", false), -- Address 0x10: Enable SGMII
-- mdioWriteInst(PHY_G, 16#09#, X"0200", false), -- Address 0x09: Advertise 1000 FD only
-- mdioWriteInst(PHY_G, 16#04#, X"0140", false), -- Address 0x04: Advertise 10/100 FD only
mdioWriteInst(PHY_G, 16#00#, x"1140", false), -- Address 0x00: Enable autoneg and full duplex

mdioWriteInst(PHY_G, 16#1F#, x"4000", true)); -- Address 0x1F: Initiate the soft restart.

constant REG0x13_IDX_C : natural := 0;
constant REG0x11_IDX_C : natural := 1;
Expand Down Expand Up @@ -118,8 +121,10 @@ begin
hdlrDone => hdlrDone,
args => args,
mdc => mdc,
mdTri => mdTri,
mdi => mdi,
mdo => mdo, phyIrq => linkIrq);
mdo => mdo,
phyIrq => linkIrq);

COMB : process(args, hdlrDone, r)
variable v : RegType;
Expand Down
103 changes: 42 additions & 61 deletions devices/Ti/dp83867/lvdsUltraScale/SgmiiDp83867LvdsUltraScale.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,14 +22,17 @@ use surf.AxiStreamPkg.all;
use surf.AxiLitePkg.all;
use surf.EthMacPkg.all;

library UNISIM;
use UNISIM.vcomponents.all;

entity SgmiiDp83867LvdsUltraScale is
generic (
TPD_G : time := 1 ns;
STABLE_CLK_FREQ_G : real := 156.25E+6;
PAUSE_EN_G : boolean := true;
JUMBO_G : boolean := true;
EN_AXIL_REG_G : boolean := false;
PHY_G : natural range 0 to 31 := 7;
PHY_G : natural range 0 to 15 := 3;
AXIS_CONFIG_G : AxiStreamConfigType := EMAC_AXIS_CONFIG_C);
port (
-- clock and reset
Expand Down Expand Up @@ -74,46 +77,64 @@ end entity SgmiiDp83867LvdsUltraScale;

architecture mapping of SgmiiDp83867LvdsUltraScale is

signal phyClock : sl;
signal phyReset : sl;

signal phyInitRst : sl;
signal phyIrq : sl;
signal phyTri : sl;
signal phyMdi : sl;
signal phyMdiSync : sl;
signal phyMdo : sl := '1';

signal extPhyRstN : sl := '0';
signal extPhyReady : sl := '0';
signal extPhyRstN : sl := '0';

signal sp10_100 : sl := '0';
signal sp100 : sl := '0';
signal initDone : sl := '0';

begin

phyClk <= phyClock;
phyRst <= phyReset;

speed10 <= sp10_100 and not sp100;
speed100 <= sp10_100 and not sp100;
speed1000 <= not sp10_100 and not sp100;

-- Tri-state driver for phyMdio
phyMdio <= 'Z' when phyMdo = '1' else '0';
U_phyMdio : IOBUF
port map (
I => phyMdo, -- 1-bit input: Buffer input
O => phyMdi, -- 1-bit output: Buffer output
IO => phyMdio, -- 1-bit inout: Buffer inout
T => phyTri); -- 1-bit input: 3-state enable input

-- Reset line of the external phy
phyRstN <= extPhyRstN;

U_SyncIrq : entity surf.Synchronizer
generic map (
TPD_G => TPD_G,
OUT_POLARITY_G => '0',
INIT_G => "11")
port map (
clk => stableClk,
dataIn => phyIrqN,
dataOut => phyIrq);

U_SyncMdi : entity surf.Synchronizer
generic map (
TPD_G => TPD_G)
port map (
clk => stableClk,
dataIn => phyMdi,
dataOut => phyMdiSync);

--------------------------------------------------------------------------
-- We must hold reset for >10ms and then wait >5ms until we may talk
-- to it (we actually wait also >10ms) which is indicated by 'extPhyReady'
-- to it (we actually wait also >10ms) which is indicated by 'phyInitRst'
--------------------------------------------------------------------------
U_PwrUpRst0 : entity surf.PwrUpRst
generic map(
TPD_G => TPD_G,
IN_POLARITY_G => '1',
OUT_POLARITY_G => '0',
DURATION_G => getTimeRatio(STABLE_CLK_FREQ_G, 100.0)) -- 10 ms reset
DURATION_G => getTimeRatio(STABLE_CLK_FREQ_G, 2.0)) -- 500 ms reset
port map (
arst => extRst,
clk => stableClk,
Expand All @@ -123,71 +144,31 @@ begin
generic map(
TPD_G => TPD_G,
IN_POLARITY_G => '0',
OUT_POLARITY_G => '0',
DURATION_G => getTimeRatio(STABLE_CLK_FREQ_G, 100.0)) -- 10 ms reset
OUT_POLARITY_G => '1',
DURATION_G => getTimeRatio(STABLE_CLK_FREQ_G, 2.0)) -- 500 ms reset
port map (
arst => extPhyRstN,
clk => stableClk,
rstOut => extPhyReady);
rstOut => phyInitRst);

----------------------------------------------------------------------
-- The MDIO controller which talks to the external PHY must be held
-- in reset until extPhyReady; it works in a different clock domain...
----------------------------------------------------------------------
U_PhyInitRstSync : entity surf.RstSync
generic map (
IN_POLARITY_G => '0',
OUT_POLARITY_G => '1')
port map (
clk => phyClock,
asyncRst => extPhyReady,
syncRst => phyInitRst);

-----------------------------------------------------------------------
-- The SaltCore does not support auto-negotiation on the SGMII link
-- (mac<->phy) - however, the DP83867ISRGZ PHY (by default) assumes it does.
-- We need to disable auto-negotiation in the PHY on the SGMII side
-- and handle link changes (aneg still enabled on copper) flagged
-- by the PHY...
-----------------------------------------------------------------------
U_PhyCtrl : entity surf.SgmiiDp83867Mdio
generic map (
TPD_G => TPD_G,
PHY_G => PHY_G,
DIV_G => getTimeRatio(STABLE_CLK_FREQ_G, 2*1.0E+6)) -- phyMdc = 1.0 MHz
port map (
clk => phyClock,
clk => stableClk,
rst => phyInitRst,
initDone => initDone,
speed_is_10_100 => sp10_100,
speed_is_100 => sp100,
linkIsUp => linkUp,
mdi => phyMdi,
mdi => phyMdiSync,
mdc => phyMdc,
mdTri => phyTri,
mdo => phyMdo,
linkIrq => phyIrq);

----------------------------------------------------
-- synchronize MDI and IRQ signals into 'clk' domain
----------------------------------------------------
U_SyncMdi : entity surf.Synchronizer
generic map (
TPD_G => TPD_G)
port map (
clk => phyClock,
dataIn => phyMdio,
dataOut => phyMdi);

U_SyncIrq : entity surf.Synchronizer
generic map (
TPD_G => TPD_G,
OUT_POLARITY_G => '0',
INIT_G => "11")
port map (
clk => phyClock,
dataIn => phyIrqN,
dataOut => phyIrq);

U_1GigE : entity surf.GigEthLvdsUltraScale
generic map (
TPD_G => TPD_G,
Expand Down Expand Up @@ -216,9 +197,9 @@ begin
speed_is_10_100 => sp10_100,
speed_is_100 => sp100,
-- PHY + MAC signals
extRst => extRst,
ethClk => phyClock,
ethRst => phyReset,
extRst => phyInitRst,
ethClk => phyClk,
ethRst => phyRst,
phyReady => phyReady,
-- SGMII / LVDS Ports
sgmiiClkP => phyClkP, -- 625 MHz
Expand Down
12 changes: 12 additions & 0 deletions protocols/mdio/rtl/MdioCore.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,7 @@ entity MdioCore is
-- MDIO interface
mdc : out sl;
mdo : out sl;
mdTri : out sl;
mdi : in sl
);
end entity MdioCore;
Expand All @@ -58,6 +59,7 @@ architecture MdioCoreImpl of MdioCore is
din : slv(15 downto 0);
count : slv( 5 downto 0);
div : slv(DIV_BITS_C - 1 downto 0);
tri : sl;
mdc : sl;
don : sl;
state : State;
Expand All @@ -68,6 +70,7 @@ architecture MdioCoreImpl of MdioCore is
din => ( others => '0' ),
count => ( others => '1' ),
div => ( others => '0' ),
tri => '1',
mdc => '0',
don => '0',
state => IDLE
Expand All @@ -76,10 +79,14 @@ architecture MdioCoreImpl of MdioCore is
signal r : RegType := REG_INIT_C;
signal rin : RegType;

-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "TRUE";

begin

mdo <= r.dataOut(32);
mdc <= r.mdc;
mdTri <= r.tri;

don <= r.don;
din <= r.din;
Expand All @@ -93,6 +100,7 @@ begin
v.div := slv( unsigned(r.div) - 1 );

if ( r.state = IDLE ) then
v.tri := '1';
if ( trg /= '0' ) then
v.state := RUN;
v.dataOut(31 downto 30) := "01"; -- start
Expand All @@ -103,6 +111,7 @@ begin
v.dataOut(16) := cmd.rdNotWr;
v.dataOut(15 downto 0) := cmd.dataOut;
v.div := toSlv(DIV_G - 1, DIV_BITS_C);
v.tri := '0';
end if;
else
if ( unsigned(r.div) = 0 ) then
Expand All @@ -119,6 +128,9 @@ begin
v.dataOut( 32 downto 1 ) := r.dataOut(31 downto 0);
v.dataOut( 0 ) := '1';
end if;
if r.count = b"01_0010" then
v.tri := cmd.rdNotWr;
end if;
else
v.din( 15 downto 1 ) := r.din (14 downto 0);
v.din( 0 ) := mdi;
Expand Down
8 changes: 8 additions & 0 deletions protocols/mdio/rtl/MdioLinkIrqHandler.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,7 @@ entity MdioLinkIrqHandler is

-- MDIO interface
mdc : out sl;
mdTri : out sl;
mdo : out sl;
mdi : in sl;

Expand Down Expand Up @@ -113,6 +114,12 @@ architecture MdioLinkIrqHandlerImpl of MdioLinkIrqHandler is
signal mdioDone : sl;
signal mdioData : slv(15 downto 0);

-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "TRUE";
-- attribute dont_touch of mdioRead : signal is "TRUE";
-- attribute dont_touch of mdioDone : signal is "TRUE";
-- attribute dont_touch of mdioData : signal is "TRUE";

begin

initDone <= r.initDone;
Expand All @@ -136,6 +143,7 @@ begin
don => mdioDone,

mdc => mdc,
mdTri => mdTri,
mdi => mdi,
mdo => mdo
);
Expand Down
2 changes: 2 additions & 0 deletions protocols/mdio/rtl/MdioSeqCore.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -75,6 +75,7 @@ entity MdioSeqCore is

-- MDIO interface
mdc : out sl;
mdTri : out sl;
mdo : out sl;
mdi : in sl
);
Expand Down Expand Up @@ -123,6 +124,7 @@ begin
don => oneDone,

mdc => mdc,
mdTri => mdTri,
mdi => mdi,
mdo => mdo
);
Expand Down

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