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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,94 @@ | ||
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| `ifdef BSV_ASSIGNMENT_DELAY | ||
| `else | ||
| `define BSV_ASSIGNMENT_DELAY | ||
| `endif | ||
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| // Dual-Ported BRAM (WRITE FIRST) | ||
| module BRAM2(CLKA, | ||
| ENA, | ||
| WEA, | ||
| ADDRA, | ||
| DIA, | ||
| DOA, | ||
| CLKB, | ||
| ENB, | ||
| WEB, | ||
| ADDRB, | ||
| DIB, | ||
| DOB | ||
| ); | ||
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| parameter PIPELINED = 0; | ||
| parameter ADDR_WIDTH = 1; | ||
| parameter DATA_WIDTH = 1; | ||
| parameter MEMSIZE = 1; | ||
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| input CLKA; | ||
| input ENA; | ||
| input WEA; | ||
| input [ADDR_WIDTH-1:0] ADDRA; | ||
| input [DATA_WIDTH-1:0] DIA; | ||
| output [DATA_WIDTH-1:0] DOA; | ||
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| input CLKB; | ||
| input ENB; | ||
| input WEB; | ||
| input [ADDR_WIDTH-1:0] ADDRB; | ||
| input [DATA_WIDTH-1:0] DIB; | ||
| output [DATA_WIDTH-1:0] DOB; | ||
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| reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ; | ||
| reg [DATA_WIDTH-1:0] DOA_R; | ||
| reg [DATA_WIDTH-1:0] DOB_R; | ||
| reg [DATA_WIDTH-1:0] DOA_R2; | ||
| reg [DATA_WIDTH-1:0] DOB_R2; | ||
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| `ifdef BSV_NO_INITIAL_BLOCKS | ||
| `else | ||
| // synopsys translate_off | ||
| integer i; | ||
| initial | ||
| begin : init_block | ||
| for (i = 0; i < MEMSIZE; i = i + 1) begin | ||
| RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } }; | ||
| end | ||
| DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; | ||
| DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; | ||
| DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; | ||
| DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; | ||
| end | ||
| // synopsys translate_on | ||
| `endif // !`ifdef BSV_NO_INITIAL_BLOCKS | ||
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| always @(posedge CLKA) begin | ||
| if (ENA) begin | ||
| if (WEA) begin | ||
| RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA; | ||
| DOA_R <= `BSV_ASSIGNMENT_DELAY DIA; | ||
| end | ||
| else begin | ||
| DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA]; | ||
| end | ||
| end | ||
| DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R; | ||
| end | ||
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| always @(posedge CLKB) begin | ||
| if (ENB) begin | ||
| if (WEB) begin | ||
| RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB; | ||
| DOB_R <= `BSV_ASSIGNMENT_DELAY DIB; | ||
| end | ||
| else begin | ||
| DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB]; | ||
| end | ||
| end | ||
| DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R; | ||
| end | ||
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| // Output drivers | ||
| assign DOA = (PIPELINED) ? DOA_R2 : DOA_R; | ||
| assign DOB = (PIPELINED) ? DOB_R2 : DOB_R; | ||
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| endmodule // BRAM2 |
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| @@ -0,0 +1,13 @@ | ||
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| module BypassWire(WGET, WVAL); | ||
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| parameter width = 1; | ||
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| input [width - 1 : 0] WVAL; | ||
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| output [width - 1 : 0] WGET; | ||
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| assign WGET = WVAL; | ||
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| endmodule |
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